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27a93dd4a9
This driver handles most voltage regulators found in X-Powers AXP PMICs. It is based on, and intended to replace, the regulator driver in TF-A. AXP PMIC regulators can be divided into 6 categories: - Switches without voltage control => fully supported. - Single linear range => fully supported. - Two linear ranges, "step" and "2 * step" => fully supported. - Two linear ranges, "step" and "5 * step" => only the first range is supported. No boards are known to use the second range. - Non-linear voltage values => fully supported. - LDOs shared with GPIO pins => not supported. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
313 lines
11 KiB
C
313 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
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/*
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2023 Samuel Holland <samuel@sholland.org>
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*/
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#include <axp_pmic.h>
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#include <dm.h>
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#include <errno.h>
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#include <dm/device-internal.h>
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#include <power/pmic.h>
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#include <power/regulator.h>
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#define NA 0xff
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struct axp_regulator_plat {
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const char *name;
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u8 enable_reg;
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u8 enable_mask;
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u8 volt_reg;
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u8 volt_mask;
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u16 min_mV;
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u16 max_mV;
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u8 step_mV;
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u8 split;
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const u16 *table;
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};
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static int axp_regulator_get_value(struct udevice *dev)
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{
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const struct axp_regulator_plat *plat = dev_get_plat(dev);
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int mV, sel;
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if (plat->volt_reg == NA)
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return -EINVAL;
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sel = pmic_reg_read(dev->parent, plat->volt_reg);
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if (sel < 0)
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return sel;
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sel &= plat->volt_mask;
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sel >>= ffs(plat->volt_mask) - 1;
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if (plat->table) {
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mV = plat->table[sel];
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} else {
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if (sel > plat->split)
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sel = plat->split + (sel - plat->split) * 2;
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mV = plat->min_mV + sel * plat->step_mV;
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}
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return mV * 1000;
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}
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static int axp_regulator_set_value(struct udevice *dev, int uV)
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{
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const struct axp_regulator_plat *plat = dev_get_plat(dev);
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int mV = uV / 1000;
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uint sel, shift;
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if (plat->volt_reg == NA)
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return -EINVAL;
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if (mV < plat->min_mV || mV > plat->max_mV)
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return -EINVAL;
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shift = ffs(plat->volt_mask) - 1;
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if (plat->table) {
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/*
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* The table must be monotonically increasing and
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* have an entry for each possible field value.
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*/
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sel = plat->volt_mask >> shift;
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while (sel && plat->table[sel] > mV)
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sel--;
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} else {
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sel = (mV - plat->min_mV) / plat->step_mV;
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if (sel > plat->split)
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sel = plat->split + (sel - plat->split) / 2;
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}
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return pmic_clrsetbits(dev->parent, plat->volt_reg,
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plat->volt_mask, sel << shift);
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}
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static int axp_regulator_get_enable(struct udevice *dev)
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{
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const struct axp_regulator_plat *plat = dev_get_plat(dev);
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int reg;
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reg = pmic_reg_read(dev->parent, plat->enable_reg);
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if (reg < 0)
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return reg;
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return (reg & plat->enable_mask) == plat->enable_mask;
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}
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static int axp_regulator_set_enable(struct udevice *dev, bool enable)
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{
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const struct axp_regulator_plat *plat = dev_get_plat(dev);
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return pmic_clrsetbits(dev->parent, plat->enable_reg,
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plat->enable_mask,
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enable ? plat->enable_mask : 0);
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}
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static const struct dm_regulator_ops axp_regulator_ops = {
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.get_value = axp_regulator_get_value,
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.set_value = axp_regulator_set_value,
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.get_enable = axp_regulator_get_enable,
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.set_enable = axp_regulator_set_enable,
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};
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static const u16 axp152_dcdc1_table[] = {
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1700, 1800, 1900, 2000, 2100, 2400, 2500, 2600,
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2700, 2800, 3000, 3100, 3200, 3300, 3400, 3500,
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};
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static const u16 axp152_aldo12_table[] = {
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1200, 1300, 1400, 1500, 1600, 1700, 1800, 1900,
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2000, 2500, 2700, 2800, 3000, 3100, 3200, 3300,
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};
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static const u16 axp152_ldo0_table[] = {
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5000, 3300, 2800, 2500,
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};
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static const struct axp_regulator_plat axp152_regulators[] = {
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{ "dcdc1", 0x12, BIT(7), 0x26, 0x0f, .table = axp152_dcdc1_table },
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{ "dcdc2", 0x12, BIT(6), 0x23, 0x3f, 700, 2275, 25, NA },
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{ "dcdc3", 0x12, BIT(5), 0x27, 0x3f, 700, 3500, 50, NA },
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{ "dcdc4", 0x12, BIT(4), 0x2b, 0x7f, 700, 3500, 25, NA },
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{ "aldo1", 0x12, BIT(3), 0x28, 0xf0, .table = axp152_aldo12_table },
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{ "aldo2", 0x12, BIT(2), 0x28, 0x0f, .table = axp152_aldo12_table },
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{ "dldo1", 0x12, BIT(1), 0x29, 0x1f, 700, 3500, 100, NA },
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{ "dldo2", 0x12, BIT(0), 0x2a, 0x1f, 700, 3500, 100, NA },
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{ "ldo0", 0x15, BIT(7), 0x15, 0x30, .table = axp152_ldo0_table },
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{ }
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};
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static const u16 axp20x_ldo4_table[] = {
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1250, 1300, 1400, 1500, 1600, 1700, 1800, 1900,
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2000, 2500, 2700, 2800, 3000, 3100, 3200, 3300,
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};
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static const struct axp_regulator_plat axp20x_regulators[] = {
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{ "dcdc2", 0x12, BIT(4), 0x23, 0x3f, 700, 2275, 25, NA },
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{ "dcdc3", 0x12, BIT(1), 0x27, 0x7f, 700, 3500, 25, NA },
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{ "ldo2", 0x12, BIT(2), 0x28, 0xf0, 1800, 3300, 100, NA },
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{ "ldo3", 0x12, BIT(6), 0x29, 0x7f, 700, 2275, 25, NA },
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{ "ldo4", 0x12, BIT(3), 0x28, 0x0f, .table = axp20x_ldo4_table },
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{ }
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};
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static const struct axp_regulator_plat axp22x_regulators[] = {
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{"dc5ldo", 0x10, BIT(0), 0x1c, 0x07, 700, 1400, 100, NA },
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{ "dcdc1", 0x10, BIT(1), 0x21, 0x1f, 1600, 3400, 100, NA },
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{ "dcdc2", 0x10, BIT(2), 0x22, 0x3f, 600, 1540, 20, NA },
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{ "dcdc3", 0x10, BIT(3), 0x23, 0x3f, 600, 1860, 20, NA },
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{ "dcdc4", 0x10, BIT(4), 0x24, 0x3f, 600, 1540, 20, NA },
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{ "dcdc5", 0x10, BIT(5), 0x25, 0x1f, 1000, 2550, 50, NA },
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{ "aldo1", 0x10, BIT(6), 0x28, 0x1f, 700, 3300, 100, NA },
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{ "aldo2", 0x10, BIT(7), 0x29, 0x1f, 700, 3300, 100, NA },
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{ "aldo3", 0x13, BIT(7), 0x2a, 0x1f, 700, 3300, 100, NA },
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{ "dldo1", 0x12, BIT(3), 0x15, 0x1f, 700, 3300, 100, NA },
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{ "dldo2", 0x12, BIT(4), 0x16, 0x1f, 700, 3300, 100, NA },
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{ "dldo3", 0x12, BIT(5), 0x17, 0x1f, 700, 3300, 100, NA },
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{ "dldo4", 0x12, BIT(6), 0x18, 0x1f, 700, 3300, 100, NA },
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{ "eldo1", 0x12, BIT(0), 0x19, 0x1f, 700, 3300, 100, NA },
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{ "eldo2", 0x12, BIT(1), 0x1a, 0x1f, 700, 3300, 100, NA },
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{ "eldo3", 0x12, BIT(2), 0x1b, 0x1f, 700, 3300, 100, NA },
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{ "dc1sw", 0x12, BIT(7), NA, NA, NA, NA, NA, NA },
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{ }
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};
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static const struct axp_regulator_plat axp803_regulators[] = {
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{ "dcdc1", 0x10, BIT(0), 0x20, 0x1f, 1600, 3400, 100, NA },
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{ "dcdc2", 0x10, BIT(1), 0x21, 0x7f, 500, 1300, 10, 70 },
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{ "dcdc3", 0x10, BIT(2), 0x22, 0x7f, 500, 1300, 10, 70 },
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{ "dcdc4", 0x10, BIT(3), 0x23, 0x7f, 500, 1300, 10, 70 },
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{ "dcdc5", 0x10, BIT(4), 0x24, 0x7f, 800, 1840, 10, 32 },
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{ "dcdc6", 0x10, BIT(5), 0x25, 0x7f, 600, 1520, 10, 50 },
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{ "aldo1", 0x13, BIT(5), 0x28, 0x1f, 700, 3300, 100, NA },
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{ "aldo2", 0x13, BIT(6), 0x29, 0x1f, 700, 3300, 100, NA },
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{ "aldo3", 0x13, BIT(7), 0x2a, 0x1f, 700, 3300, 100, NA },
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{ "dldo1", 0x12, BIT(3), 0x15, 0x1f, 700, 3300, 100, NA },
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{ "dldo2", 0x12, BIT(4), 0x16, 0x1f, 700, 4200, 100, 27 },
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{ "dldo3", 0x12, BIT(5), 0x17, 0x1f, 700, 3300, 100, NA },
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{ "dldo4", 0x12, BIT(6), 0x18, 0x1f, 700, 3300, 100, NA },
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{ "eldo1", 0x12, BIT(0), 0x19, 0x1f, 700, 1900, 50, NA },
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{ "eldo2", 0x12, BIT(1), 0x1a, 0x1f, 700, 1900, 50, NA },
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{ "eldo3", 0x12, BIT(2), 0x1b, 0x1f, 700, 1900, 50, NA },
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{ "fldo1", 0x13, BIT(2), 0x1c, 0x0f, 700, 1450, 50, NA },
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{ "fldo2", 0x13, BIT(3), 0x1d, 0x0f, 700, 1450, 50, NA },
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{ "dc1sw", 0x12, BIT(7), NA, NA, NA, NA, NA, NA },
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{ }
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};
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/*
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* The "dcdcd" split changes the step size by a factor of 5, not 2;
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* disallow values above the split to maintain accuracy.
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*/
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static const struct axp_regulator_plat axp806_regulators[] = {
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{ "dcdca", 0x10, BIT(0), 0x12, 0x7f, 600, 1520, 10, 50 },
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{ "dcdcb", 0x10, BIT(1), 0x13, 0x1f, 1000, 2550, 50, NA },
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{ "dcdcc", 0x10, BIT(2), 0x14, 0x7f, 600, 1520, 10, 50 },
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{ "dcdcd", 0x10, BIT(3), 0x15, 0x3f, 600, 1500, 20, NA },
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{ "dcdce", 0x10, BIT(4), 0x16, 0x1f, 1100, 3400, 100, NA },
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{ "aldo1", 0x10, BIT(5), 0x17, 0x1f, 700, 3300, 100, NA },
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{ "aldo2", 0x10, BIT(6), 0x18, 0x1f, 700, 3300, 100, NA },
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{ "aldo3", 0x10, BIT(7), 0x19, 0x1f, 700, 3300, 100, NA },
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{ "bldo1", 0x11, BIT(0), 0x20, 0x0f, 700, 1900, 100, NA },
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{ "bldo2", 0x11, BIT(1), 0x21, 0x0f, 700, 1900, 100, NA },
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{ "bldo3", 0x11, BIT(2), 0x22, 0x0f, 700, 1900, 100, NA },
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{ "bldo4", 0x11, BIT(3), 0x23, 0x0f, 700, 1900, 100, NA },
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{ "cldo1", 0x11, BIT(4), 0x24, 0x1f, 700, 3300, 100, NA },
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{ "cldo2", 0x11, BIT(5), 0x25, 0x1f, 700, 4200, 100, 27 },
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{ "cldo3", 0x11, BIT(6), 0x26, 0x1f, 700, 3300, 100, NA },
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{ "sw", 0x11, BIT(7), NA, NA, NA, NA, NA, NA },
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{ }
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};
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/*
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* The "dcdc4" split changes the step size by a factor of 5, not 2;
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* disallow values above the split to maintain accuracy.
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*/
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static const struct axp_regulator_plat axp809_regulators[] = {
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{"dc5ldo", 0x10, BIT(0), 0x1c, 0x07, 700, 1400, 100, NA },
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{ "dcdc1", 0x10, BIT(1), 0x21, 0x1f, 1600, 3400, 100, NA },
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{ "dcdc2", 0x10, BIT(2), 0x22, 0x3f, 600, 1540, 20, NA },
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{ "dcdc3", 0x10, BIT(3), 0x23, 0x3f, 600, 1860, 20, NA },
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{ "dcdc4", 0x10, BIT(4), 0x24, 0x3f, 600, 1540, 20, NA },
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{ "dcdc5", 0x10, BIT(5), 0x25, 0x1f, 1000, 2550, 50, NA },
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{ "aldo1", 0x10, BIT(6), 0x28, 0x1f, 700, 3300, 100, NA },
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{ "aldo2", 0x10, BIT(7), 0x29, 0x1f, 700, 3300, 100, NA },
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{ "aldo3", 0x12, BIT(5), 0x2a, 0x1f, 700, 3300, 100, NA },
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{ "dldo1", 0x12, BIT(3), 0x15, 0x1f, 700, 3300, 100, NA },
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{ "dldo2", 0x12, BIT(4), 0x16, 0x1f, 700, 3300, 100, NA },
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{ "eldo1", 0x12, BIT(0), 0x19, 0x1f, 700, 3300, 100, NA },
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{ "eldo2", 0x12, BIT(1), 0x1a, 0x1f, 700, 3300, 100, NA },
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{ "eldo3", 0x12, BIT(2), 0x1b, 0x1f, 700, 3300, 100, NA },
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{ "sw", 0x12, BIT(6), NA, NA, NA, NA, NA, NA },
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{ "dc1sw", 0x12, BIT(7), NA, NA, NA, NA, NA, NA },
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{ }
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};
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static const struct axp_regulator_plat axp813_regulators[] = {
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{ "dcdc1", 0x10, BIT(0), 0x20, 0x1f, 1600, 3400, 100, NA },
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{ "dcdc2", 0x10, BIT(1), 0x21, 0x7f, 500, 1300, 10, 70 },
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{ "dcdc3", 0x10, BIT(2), 0x22, 0x7f, 500, 1300, 10, 70 },
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{ "dcdc4", 0x10, BIT(3), 0x23, 0x7f, 500, 1300, 10, 70 },
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{ "dcdc5", 0x10, BIT(4), 0x24, 0x7f, 800, 1840, 10, 32 },
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{ "dcdc6", 0x10, BIT(5), 0x25, 0x7f, 600, 1520, 10, 50 },
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{ "dcdc7", 0x10, BIT(6), 0x26, 0x7f, 600, 1520, 10, 50 },
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{ "aldo1", 0x13, BIT(5), 0x28, 0x1f, 700, 3300, 100, NA },
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{ "aldo2", 0x13, BIT(6), 0x29, 0x1f, 700, 3300, 100, NA },
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{ "aldo3", 0x13, BIT(7), 0x2a, 0x1f, 700, 3300, 100, NA },
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{ "dldo1", 0x12, BIT(3), 0x15, 0x1f, 700, 3300, 100, NA },
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{ "dldo2", 0x12, BIT(4), 0x16, 0x1f, 700, 4200, 100, 27 },
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{ "dldo3", 0x12, BIT(5), 0x17, 0x1f, 700, 3300, 100, NA },
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{ "dldo4", 0x12, BIT(6), 0x18, 0x1f, 700, 3300, 100, NA },
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{ "eldo1", 0x12, BIT(0), 0x19, 0x1f, 700, 1900, 50, NA },
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{ "eldo2", 0x12, BIT(1), 0x1a, 0x1f, 700, 1900, 50, NA },
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{ "eldo3", 0x12, BIT(2), 0x1b, 0x1f, 700, 1900, 50, NA },
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{ "fldo1", 0x13, BIT(2), 0x1c, 0x0f, 700, 1450, 50, NA },
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{ "fldo2", 0x13, BIT(3), 0x1d, 0x0f, 700, 1450, 50, NA },
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{ "fldo3", 0x13, BIT(4), NA, NA, NA, NA, NA, NA },
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{ }
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};
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static const struct axp_regulator_plat *const axp_regulators[] = {
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[AXP152_ID] = axp152_regulators,
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[AXP202_ID] = axp20x_regulators,
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[AXP209_ID] = axp20x_regulators,
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[AXP221_ID] = axp22x_regulators,
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[AXP223_ID] = axp22x_regulators,
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[AXP803_ID] = axp803_regulators,
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[AXP806_ID] = axp806_regulators,
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[AXP809_ID] = axp809_regulators,
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[AXP813_ID] = axp813_regulators,
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};
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static int axp_regulator_bind(struct udevice *dev)
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{
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struct dm_regulator_uclass_plat *uc_plat = dev_get_uclass_plat(dev);
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ulong id = dev_get_driver_data(dev->parent);
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const struct axp_regulator_plat *plat;
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for (plat = axp_regulators[id]; plat && plat->name; plat++)
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if (!strcmp(plat->name, dev->name))
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break;
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if (!plat || !plat->name)
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return -ENODEV;
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dev_set_plat(dev, (void *)plat);
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if (plat->volt_reg == NA)
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uc_plat->type = REGULATOR_TYPE_FIXED;
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else if (!strncmp(plat->name, "dcdc", strlen("dcdc")))
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uc_plat->type = REGULATOR_TYPE_BUCK;
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else
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uc_plat->type = REGULATOR_TYPE_LDO;
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return 0;
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}
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U_BOOT_DRIVER(axp_regulator) = {
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.name = "axp_regulator",
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.id = UCLASS_REGULATOR,
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.bind = axp_regulator_bind,
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.ops = &axp_regulator_ops,
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};
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