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Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Francois Bedard <fbedard@synopsys.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Heiko Schocher <hs@denx.de>
28 lines
1.3 KiB
Plaintext
28 lines
1.3 KiB
Plaintext
Synopsys' DesignWare(r) ARC(r) Processors are a family of 32-bit CPUs
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that SoC designers can optimize for a wide range of uses, from deeply embedded
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to high-performance host applications.
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More information on ARC cores avaialble here:
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http://www.synopsys.com/IP/ProcessorIP/ARCProcessors/Pages/default.aspx
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Designers can differentiate their products by using patented configuration
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technology to tailor each ARC processor instance to meet specific performance,
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power and area requirements.
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The DesignWare ARC processors are also extendable, allowing designers to add
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their own custom instructions that dramatically increase performance.
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Synopsys' ARC processors have been used by over 170 customers worldwide who
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collectively ship more than 1 billion ARC-based chips annually.
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All DesignWare ARC processors utilize a 16-/32-bit ISA that provides excellent
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performance and code density for embedded and host SoC applications.
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The RISC microprocessors are synthesizable and can be implemented in any foundry
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or process, and are supported by a complete suite of development tools.
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The ARC GNU toolchain with support for all ARC Processors can be downloaded
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from here (available pre-built toolchains as well):
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https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases
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