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a4275f5e52
This is easier to deal with when using generic code since it allows us to use a register index instead of naming each register. Adjust it, adding an enum to improve readability. Signed-off-by: Simon Glass <sjg@chromium.org>
94 lines
1.4 KiB
C
94 lines
1.4 KiB
C
/*
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* Copyright (c) 2015 Google, Inc
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*
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* Copyright 2014 Rockchip Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_PMU_RK3288_H
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#define _ASM_ARCH_PMU_RK3288_H
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struct rk3288_pmu {
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u32 wakeup_cfg[2];
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u32 pwrdn_con;
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u32 pwrdn_st;
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u32 idle_req;
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u32 idle_st;
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u32 pwrmode_con;
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u32 pwr_state;
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u32 osc_cnt;
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u32 pll_cnt;
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u32 stabl_cnt;
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u32 ddr0io_pwron_cnt;
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u32 ddr1io_pwron_cnt;
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u32 core_pwrdn_cnt;
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u32 core_pwrup_cnt;
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u32 gpu_pwrdn_cnt;
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u32 gpu_pwrup_cnt;
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u32 wakeup_rst_clr_cnt;
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u32 sft_con;
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u32 ddr_sref_st;
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u32 int_con;
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u32 int_st;
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u32 boot_addr_sel;
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u32 grf_con;
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u32 gpio_sr;
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u32 gpio0pull[3];
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u32 gpio0drv[3];
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u32 gpio_op;
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u32 gpio0_sel18; /* 0x80 */
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u32 gpio0_iomux[4]; /* a, b, c, d */
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u32 sys_reg[4];
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};
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check_member(rk3288_pmu, sys_reg[3], 0x00a0);
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enum {
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PMU_GPIO0_A = 0,
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PMU_GPIO0_B,
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PMU_GPIO0_C,
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PMU_GPIO0_D,
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};
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/* PMU_GPIO0_B_IOMUX */
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enum {
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GPIO0_B7_SHIFT = 14,
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GPIO0_B7_MASK = 1,
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GPIO0_B7_GPIOB7 = 0,
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GPIO0_B7_I2C0PMU_SDA,
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GPIO0_B5_SHIFT = 10,
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GPIO0_B5_MASK = 1,
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GPIO0_B5_GPIOB5 = 0,
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GPIO0_B5_CLK_27M,
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GPIO0_B2_SHIFT = 4,
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GPIO0_B2_MASK = 1,
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GPIO0_B2_GPIOB2 = 0,
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GPIO0_B2_TSADC_INT,
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};
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/* PMU_GPIO0_C_IOMUX */
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enum {
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GPIO0_C1_SHIFT = 2,
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GPIO0_C1_MASK = 3,
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GPIO0_C1_GPIOC1 = 0,
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GPIO0_C1_TEST_CLKOUT,
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GPIO0_C1_CLKT1_27M,
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GPIO0_C0_SHIFT = 0,
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GPIO0_C0_MASK = 1,
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GPIO0_C0_GPIOC0 = 0,
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GPIO0_C0_I2C0PMU_SCL,
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};
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#endif
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