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https://github.com/smaeul/u-boot.git
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9ef89ea9b0
Add basic i.MX8ULP support For the MMU part, Using a simple way the calculate the MMU size to avoid default heavy calcaulation. And align address and size in the table settings to 2MB or 4GB as much as possible. So we can reduce the 4K page allocations in MMU table which will spends much time in create the page table Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
290 lines
6.0 KiB
C
290 lines
6.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2021 NXP
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*/
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/armv8/mmu.h>
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#include <asm/mach-imx/boot_mode.h>
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DECLARE_GLOBAL_DATA_PTR;
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u32 get_cpu_rev(void)
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{
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return (MXC_CPU_IMX8ULP << 12) | CHIP_REV_1_0;
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}
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enum bt_mode get_boot_mode(void)
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{
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u32 bt0_cfg = 0;
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bt0_cfg = readl(CMC0_RBASE + 0x80);
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bt0_cfg &= (BT0CFG_LPBOOT_MASK | BT0CFG_DUALBOOT_MASK);
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if (!(bt0_cfg & BT0CFG_LPBOOT_MASK)) {
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/* No low power boot */
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if (bt0_cfg & BT0CFG_DUALBOOT_MASK)
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return DUAL_BOOT;
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else
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return SINGLE_BOOT;
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}
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return LOW_POWER_BOOT;
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}
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#define CMC_SRS_TAMPER BIT(31)
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#define CMC_SRS_SECURITY BIT(30)
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#define CMC_SRS_TZWDG BIT(29)
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#define CMC_SRS_JTAG_RST BIT(28)
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#define CMC_SRS_CORE1 BIT(16)
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#define CMC_SRS_LOCKUP BIT(15)
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#define CMC_SRS_SW BIT(14)
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#define CMC_SRS_WDG BIT(13)
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#define CMC_SRS_PIN_RESET BIT(8)
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#define CMC_SRS_WARM BIT(4)
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#define CMC_SRS_HVD BIT(3)
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#define CMC_SRS_LVD BIT(2)
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#define CMC_SRS_POR BIT(1)
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#define CMC_SRS_WUP BIT(0)
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static u32 reset_cause = -1;
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static char *get_reset_cause(char *ret)
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{
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u32 cause1, cause = 0, srs = 0;
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void __iomem *reg_ssrs = (void __iomem *)(CMC1_BASE_ADDR + 0x88);
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void __iomem *reg_srs = (void __iomem *)(CMC1_BASE_ADDR + 0x80);
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if (!ret)
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return "null";
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srs = readl(reg_srs);
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cause1 = readl(reg_ssrs);
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reset_cause = cause1;
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cause = cause1 & (CMC_SRS_POR | CMC_SRS_WUP | CMC_SRS_WARM);
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switch (cause) {
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case CMC_SRS_POR:
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sprintf(ret, "%s", "POR");
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break;
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case CMC_SRS_WUP:
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sprintf(ret, "%s", "WUP");
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break;
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case CMC_SRS_WARM:
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cause = cause1 & (CMC_SRS_WDG | CMC_SRS_SW |
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CMC_SRS_JTAG_RST);
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switch (cause) {
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case CMC_SRS_WDG:
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sprintf(ret, "%s", "WARM-WDG");
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break;
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case CMC_SRS_SW:
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sprintf(ret, "%s", "WARM-SW");
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break;
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case CMC_SRS_JTAG_RST:
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sprintf(ret, "%s", "WARM-JTAG");
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break;
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default:
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sprintf(ret, "%s", "WARM-UNKN");
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break;
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}
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break;
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default:
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sprintf(ret, "%s-%X", "UNKN", cause1);
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break;
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}
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debug("[%X] SRS[%X] %X - ", cause1, srs, srs ^ cause1);
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return ret;
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}
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#if defined(CONFIG_DISPLAY_CPUINFO)
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const char *get_imx_type(u32 imxtype)
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{
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return "8ULP";
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}
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int print_cpuinfo(void)
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{
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u32 cpurev;
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char cause[18];
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cpurev = get_cpu_rev();
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printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
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get_imx_type((cpurev & 0xFF000) >> 12),
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(cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0,
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mxc_get_clock(MXC_ARM_CLK) / 1000000);
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printf("Reset cause: %s\n", get_reset_cause(cause));
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printf("Boot mode: ");
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switch (get_boot_mode()) {
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case LOW_POWER_BOOT:
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printf("Low power boot\n");
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break;
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case DUAL_BOOT:
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printf("Dual boot\n");
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break;
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case SINGLE_BOOT:
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default:
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printf("Single boot\n");
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break;
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}
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return 0;
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}
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#endif
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void init_wdog(void)
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{
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/* TODO */
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}
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static struct mm_region imx8ulp_arm64_mem_map[] = {
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{
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/* ROM */
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.virt = 0x0,
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.phys = 0x0,
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.size = 0x40000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_OUTER_SHARE
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},
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{
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/* FLEXSPI0 */
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.virt = 0x04000000,
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.phys = 0x04000000,
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.size = 0x08000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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},
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{
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/* SSRAM (align with 2M) */
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.virt = 0x1FE00000UL,
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.phys = 0x1FE00000UL,
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.size = 0x400000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_OUTER_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* SRAM1 (align with 2M) */
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.virt = 0x21000000UL,
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.phys = 0x21000000UL,
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.size = 0x200000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_OUTER_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* SRAM0 (align with 2M) */
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.virt = 0x22000000UL,
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.phys = 0x22000000UL,
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.size = 0x200000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_OUTER_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* Peripherals */
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.virt = 0x27000000UL,
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.phys = 0x27000000UL,
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.size = 0x3000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* Peripherals */
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.virt = 0x2D000000UL,
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.phys = 0x2D000000UL,
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.size = 0x1600000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* FLEXSPI1-2 */
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.virt = 0x40000000UL,
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.phys = 0x40000000UL,
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.size = 0x40000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* DRAM1 */
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.virt = 0x80000000UL,
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.phys = 0x80000000UL,
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.size = PHYS_SDRAM_SIZE,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_OUTER_SHARE
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}, {
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/*
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* empty entrie to split table entry 5
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* if needed when TEEs are used
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*/
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0,
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = imx8ulp_arm64_mem_map;
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/* simplify the page table size to enhance boot speed */
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#define MAX_PTE_ENTRIES 512
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#define MAX_MEM_MAP_REGIONS 16
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u64 get_page_table_size(void)
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{
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u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
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u64 size = 0;
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/*
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* For each memory region, the max table size:
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* 2 level 3 tables + 2 level 2 tables + 1 level 1 table
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*/
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size = (2 + 2 + 1) * one_pt * MAX_MEM_MAP_REGIONS + one_pt;
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/*
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* We need to duplicate our page table once to have an emergency pt to
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* resort to when splitting page tables later on
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*/
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size *= 2;
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/*
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* We may need to split page tables later on if dcache settings change,
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* so reserve up to 4 (random pick) page tables for that.
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*/
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size += one_pt * 4;
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return size;
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}
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void enable_caches(void)
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{
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/* TODO: add TEE memmap region */
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icache_enable();
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dcache_enable();
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}
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int dram_init(void)
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{
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gd->ram_size = PHYS_SDRAM_SIZE;
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return 0;
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}
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#ifdef CONFIG_SERIAL_TAG
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void get_board_serial(struct tag_serialnr *serialnr)
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{
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/* TODO */
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}
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#endif
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int arch_cpu_init(void)
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{
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return 0;
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}
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