mirror of
https://github.com/smaeul/u-boot.git
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301 lines
10 KiB
C
301 lines
10 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright 2019 NXP
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*/
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#ifndef __DT_BINDINGS_CLOCK_IMX8MP_H
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#define __DT_BINDINGS_CLOCK_IMX8MP_H
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#define IMX8MP_CLK_DUMMY 0
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#define IMX8MP_CLK_32K 1
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#define IMX8MP_CLK_24M 2
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#define IMX8MP_OSC_HDMI_CLK 3
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#define IMX8MP_CLK_EXT1 4
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#define IMX8MP_CLK_EXT2 5
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#define IMX8MP_CLK_EXT3 6
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#define IMX8MP_CLK_EXT4 7
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#define IMX8MP_AUDIO_PLL1_REF_SEL 8
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#define IMX8MP_AUDIO_PLL2_REF_SEL 9
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#define IMX8MP_VIDEO_PLL1_REF_SEL 10
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#define IMX8MP_DRAM_PLL_REF_SEL 11
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#define IMX8MP_GPU_PLL_REF_SEL 12
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#define IMX8MP_VPU_PLL_REF_SEL 13
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#define IMX8MP_ARM_PLL_REF_SEL 14
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#define IMX8MP_SYS_PLL1_REF_SEL 15
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#define IMX8MP_SYS_PLL2_REF_SEL 16
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#define IMX8MP_SYS_PLL3_REF_SEL 17
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#define IMX8MP_AUDIO_PLL1 18
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#define IMX8MP_AUDIO_PLL2 19
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#define IMX8MP_VIDEO_PLL1 20
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#define IMX8MP_DRAM_PLL 21
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#define IMX8MP_GPU_PLL 22
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#define IMX8MP_VPU_PLL 23
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#define IMX8MP_ARM_PLL 24
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#define IMX8MP_SYS_PLL1 25
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#define IMX8MP_SYS_PLL2 26
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#define IMX8MP_SYS_PLL3 27
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#define IMX8MP_AUDIO_PLL1_BYPASS 28
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#define IMX8MP_AUDIO_PLL2_BYPASS 29
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#define IMX8MP_VIDEO_PLL1_BYPASS 30
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#define IMX8MP_DRAM_PLL_BYPASS 31
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#define IMX8MP_GPU_PLL_BYPASS 32
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#define IMX8MP_VPU_PLL_BYPASS 33
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#define IMX8MP_ARM_PLL_BYPASS 34
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#define IMX8MP_SYS_PLL1_BYPASS 35
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#define IMX8MP_SYS_PLL2_BYPASS 36
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#define IMX8MP_SYS_PLL3_BYPASS 37
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#define IMX8MP_AUDIO_PLL1_OUT 38
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#define IMX8MP_AUDIO_PLL2_OUT 39
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#define IMX8MP_VIDEO_PLL1_OUT 40
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#define IMX8MP_DRAM_PLL_OUT 41
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#define IMX8MP_GPU_PLL_OUT 42
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#define IMX8MP_VPU_PLL_OUT 43
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#define IMX8MP_ARM_PLL_OUT 44
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#define IMX8MP_SYS_PLL1_OUT 45
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#define IMX8MP_SYS_PLL2_OUT 46
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#define IMX8MP_SYS_PLL3_OUT 47
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#define IMX8MP_SYS_PLL1_40M 48
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#define IMX8MP_SYS_PLL1_80M 49
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#define IMX8MP_SYS_PLL1_100M 50
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#define IMX8MP_SYS_PLL1_133M 51
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#define IMX8MP_SYS_PLL1_160M 52
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#define IMX8MP_SYS_PLL1_200M 53
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#define IMX8MP_SYS_PLL1_266M 54
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#define IMX8MP_SYS_PLL1_400M 55
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#define IMX8MP_SYS_PLL1_800M 56
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#define IMX8MP_SYS_PLL2_50M 57
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#define IMX8MP_SYS_PLL2_100M 58
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#define IMX8MP_SYS_PLL2_125M 59
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#define IMX8MP_SYS_PLL2_166M 60
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#define IMX8MP_SYS_PLL2_200M 61
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#define IMX8MP_SYS_PLL2_250M 62
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#define IMX8MP_SYS_PLL2_333M 63
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#define IMX8MP_SYS_PLL2_500M 64
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#define IMX8MP_SYS_PLL2_1000M 65
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#define IMX8MP_CLK_A53_SRC 66
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#define IMX8MP_CLK_M7_SRC 67
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#define IMX8MP_CLK_ML_SRC 68
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#define IMX8MP_CLK_GPU3D_CORE_SRC 69
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#define IMX8MP_CLK_GPU3D_SHADER_SRC 70
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#define IMX8MP_CLK_GPU2D_SRC 71
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#define IMX8MP_CLK_AUDIO_AXI_SRC 72
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#define IMX8MP_CLK_HSIO_AXI_SRC 73
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#define IMX8MP_CLK_MEDIA_ISP_SRC 74
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#define IMX8MP_CLK_A53_CG 75
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#define IMX8MP_CLK_M4_CG 76
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#define IMX8MP_CLK_ML_CG 77
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#define IMX8MP_CLK_GPU3D_CORE_CG 78
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#define IMX8MP_CLK_GPU3D_SHADER_CG 79
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#define IMX8MP_CLK_GPU2D_CG 80
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#define IMX8MP_CLK_AUDIO_AXI_CG 81
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#define IMX8MP_CLK_HSIO_AXI_CG 82
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#define IMX8MP_CLK_MEDIA_ISP_CG 83
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#define IMX8MP_CLK_A53_DIV 84
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#define IMX8MP_CLK_M7_DIV 85
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#define IMX8MP_CLK_ML_DIV 86
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#define IMX8MP_CLK_GPU3D_CORE_DIV 87
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#define IMX8MP_CLK_GPU3D_SHADER_DIV 88
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#define IMX8MP_CLK_GPU2D_DIV 89
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#define IMX8MP_CLK_AUDIO_AXI_DIV 90
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#define IMX8MP_CLK_HSIO_AXI_DIV 91
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#define IMX8MP_CLK_MEDIA_ISP_DIV 92
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#define IMX8MP_CLK_MAIN_AXI 93
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#define IMX8MP_CLK_ENET_AXI 94
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#define IMX8MP_CLK_NAND_USDHC_BUS 95
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#define IMX8MP_CLK_VPU_BUS 96
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#define IMX8MP_CLK_MEDIA_AXI 97
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#define IMX8MP_CLK_MEDIA_APB 98
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#define IMX8MP_CLK_HDMI_APB 99
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#define IMX8MP_CLK_HDMI_AXI 100
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#define IMX8MP_CLK_GPU_AXI 101
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#define IMX8MP_CLK_GPU_AHB 102
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#define IMX8MP_CLK_NOC 103
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#define IMX8MP_CLK_NOC_IO 104
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#define IMX8MP_CLK_ML_AXI 105
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#define IMX8MP_CLK_ML_AHB 106
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#define IMX8MP_CLK_AHB 107
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#define IMX8MP_CLK_AUDIO_AHB 108
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#define IMX8MP_CLK_MIPI_DSI_ESC_RX 109
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#define IMX8MP_CLK_IPG_ROOT 110
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#define IMX8MP_CLK_IPG_AUDIO_ROOT 111
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#define IMX8MP_CLK_DRAM_ALT 112
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#define IMX8MP_CLK_DRAM_APB 113
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#define IMX8MP_CLK_VPU_G1 114
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#define IMX8MP_CLK_VPU_G2 115
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#define IMX8MP_CLK_CAN1 116
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#define IMX8MP_CLK_CAN2 117
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#define IMX8MP_CLK_MEMREPAIR 118
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#define IMX8MP_CLK_PCIE_PHY 119
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#define IMX8MP_CLK_PCIE_AUX 120
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#define IMX8MP_CLK_I2C5 121
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#define IMX8MP_CLK_I2C6 122
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#define IMX8MP_CLK_SAI1 123
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#define IMX8MP_CLK_SAI2 124
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#define IMX8MP_CLK_SAI3 125
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#define IMX8MP_CLK_SAI4 126
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#define IMX8MP_CLK_SAI5 127
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#define IMX8MP_CLK_SAI6 128
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#define IMX8MP_CLK_ENET_QOS 129
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#define IMX8MP_CLK_ENET_QOS_TIMER 130
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#define IMX8MP_CLK_ENET_REF 131
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#define IMX8MP_CLK_ENET_TIMER 132
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#define IMX8MP_CLK_ENET_PHY_REF 133
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#define IMX8MP_CLK_NAND 134
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#define IMX8MP_CLK_QSPI 135
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#define IMX8MP_CLK_USDHC1 136
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#define IMX8MP_CLK_USDHC2 137
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#define IMX8MP_CLK_I2C1 138
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#define IMX8MP_CLK_I2C2 139
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#define IMX8MP_CLK_I2C3 140
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#define IMX8MP_CLK_I2C4 141
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#define IMX8MP_CLK_UART1 142
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#define IMX8MP_CLK_UART2 143
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#define IMX8MP_CLK_UART3 144
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#define IMX8MP_CLK_UART4 145
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#define IMX8MP_CLK_USB_CORE_REF 146
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#define IMX8MP_CLK_USB_PHY_REF 147
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#define IMX8MP_CLK_GIC 148
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#define IMX8MP_CLK_ECSPI1 149
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#define IMX8MP_CLK_ECSPI2 150
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#define IMX8MP_CLK_PWM1 151
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#define IMX8MP_CLK_PWM2 152
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#define IMX8MP_CLK_PWM3 153
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#define IMX8MP_CLK_PWM4 154
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#define IMX8MP_CLK_GPT1 155
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#define IMX8MP_CLK_GPT2 156
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#define IMX8MP_CLK_GPT3 157
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#define IMX8MP_CLK_GPT4 158
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#define IMX8MP_CLK_GPT5 159
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#define IMX8MP_CLK_GPT6 160
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#define IMX8MP_CLK_TRACE 161
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#define IMX8MP_CLK_WDOG 162
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#define IMX8MP_CLK_WRCLK 163
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#define IMX8MP_CLK_IPP_DO_CLKO1 164
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#define IMX8MP_CLK_IPP_DO_CLKO2 165
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#define IMX8MP_CLK_HDMI_FDCC_TST 166
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#define IMX8MP_CLK_HDMI_27M 167
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#define IMX8MP_CLK_HDMI_REF_266M 168
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#define IMX8MP_CLK_USDHC3 169
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#define IMX8MP_CLK_MEDIA_CAM1_PIX 170
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#define IMX8MP_CLK_MEDIA_MIPI_PHY1_REF 171
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#define IMX8MP_CLK_MEDIA_DISP1_PIX 172
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#define IMX8MP_CLK_MEDIA_CAM2_PIX 173
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#define IMX8MP_CLK_MEDIA_MIPI_PHY2_REF 174
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#define IMX8MP_CLK_MEDIA_MIPI_CSI2_ESC 175
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#define IMX8MP_CLK_PCIE2_CTRL 176
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#define IMX8MP_CLK_PCIE2_PHY 177
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#define IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE 178
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#define IMX8MP_CLK_ECSPI3 179
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#define IMX8MP_CLK_PDM 180
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#define IMX8MP_CLK_VPU_VC8000E 181
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#define IMX8MP_CLK_SAI7 182
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#define IMX8MP_CLK_GPC_ROOT 183
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#define IMX8MP_CLK_ANAMIX_ROOT 184
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#define IMX8MP_CLK_CPU_ROOT 185
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#define IMX8MP_CLK_CSU_ROOT 186
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#define IMX8MP_CLK_DEBUG_ROOT 187
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#define IMX8MP_CLK_DRAM1_ROOT 188
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#define IMX8MP_CLK_ECSPI1_ROOT 189
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#define IMX8MP_CLK_ECSPI2_ROOT 190
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#define IMX8MP_CLK_ECSPI3_ROOT 191
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#define IMX8MP_CLK_ENET1_ROOT 192
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#define IMX8MP_CLK_GPIO1_ROOT 193
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#define IMX8MP_CLK_GPIO2_ROOT 194
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#define IMX8MP_CLK_GPIO3_ROOT 195
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#define IMX8MP_CLK_GPIO4_ROOT 196
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#define IMX8MP_CLK_GPIO5_ROOT 197
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#define IMX8MP_CLK_GPT1_ROOT 198
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#define IMX8MP_CLK_GPT2_ROOT 199
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#define IMX8MP_CLK_GPT3_ROOT 200
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#define IMX8MP_CLK_GPT4_ROOT 201
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#define IMX8MP_CLK_GPT5_ROOT 202
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#define IMX8MP_CLK_GPT6_ROOT 203
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#define IMX8MP_CLK_HS_ROOT 204
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#define IMX8MP_CLK_I2C1_ROOT 205
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#define IMX8MP_CLK_I2C2_ROOT 206
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#define IMX8MP_CLK_I2C3_ROOT 207
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#define IMX8MP_CLK_I2C4_ROOT 208
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#define IMX8MP_CLK_IOMUX_ROOT 209
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#define IMX8MP_CLK_IPMUX1_ROOT 210
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#define IMX8MP_CLK_IPMUX2_ROOT 211
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#define IMX8MP_CLK_IPMUX3_ROOT 212
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#define IMX8MP_CLK_MU_ROOT 213
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#define IMX8MP_CLK_OCOTP_ROOT 214
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#define IMX8MP_CLK_OCRAM_ROOT 215
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#define IMX8MP_CLK_OCRAM_S_ROOT 216
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#define IMX8MP_CLK_PCIE_ROOT 217
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#define IMX8MP_CLK_PERFMON1_ROOT 218
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#define IMX8MP_CLK_PERFMON2_ROOT 219
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#define IMX8MP_CLK_PWM1_ROOT 220
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#define IMX8MP_CLK_PWM2_ROOT 221
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#define IMX8MP_CLK_PWM3_ROOT 222
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#define IMX8MP_CLK_PWM4_ROOT 223
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#define IMX8MP_CLK_QOS_ROOT 224
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#define IMX8MP_CLK_QOS_ENET_ROOT 225
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#define IMX8MP_CLK_QSPI_ROOT 226
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#define IMX8MP_CLK_NAND_ROOT 227
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#define IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK 228
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#define IMX8MP_CLK_RDC_ROOT 229
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#define IMX8MP_CLK_ROM_ROOT 230
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#define IMX8MP_CLK_I2C5_ROOT 231
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#define IMX8MP_CLK_I2C6_ROOT 232
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#define IMX8MP_CLK_CAN1_ROOT 233
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#define IMX8MP_CLK_CAN2_ROOT 234
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#define IMX8MP_CLK_SCTR_ROOT 235
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#define IMX8MP_CLK_SDMA1_ROOT 236
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#define IMX8MP_CLK_ENET_QOS_ROOT 237
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#define IMX8MP_CLK_SEC_DEBUG_ROOT 238
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#define IMX8MP_CLK_SEMA1_ROOT 239
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#define IMX8MP_CLK_SEMA2_ROOT 240
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#define IMX8MP_CLK_IRQ_STEER_ROOT 241
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#define IMX8MP_CLK_SIM_ENET_ROOT 242
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#define IMX8MP_CLK_SIM_M_ROOT 243
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#define IMX8MP_CLK_SIM_MAIN_ROOT 244
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#define IMX8MP_CLK_SIM_S_ROOT 245
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#define IMX8MP_CLK_SIM_WAKEUP_ROOT 246
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#define IMX8MP_CLK_GPU2D_ROOT 247
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#define IMX8MP_CLK_GPU3D_ROOT 248
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#define IMX8MP_CLK_SNVS_ROOT 249
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#define IMX8MP_CLK_TRACE_ROOT 250
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#define IMX8MP_CLK_UART1_ROOT 251
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#define IMX8MP_CLK_UART2_ROOT 252
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#define IMX8MP_CLK_UART3_ROOT 253
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#define IMX8MP_CLK_UART4_ROOT 254
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#define IMX8MP_CLK_USB_ROOT 255
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#define IMX8MP_CLK_USB_PHY_ROOT 256
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#define IMX8MP_CLK_USDHC1_ROOT 257
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#define IMX8MP_CLK_USDHC2_ROOT 258
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#define IMX8MP_CLK_WDOG1_ROOT 259
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#define IMX8MP_CLK_WDOG2_ROOT 260
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#define IMX8MP_CLK_WDOG3_ROOT 261
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#define IMX8MP_CLK_VPU_G1_ROOT 262
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#define IMX8MP_CLK_GPU_ROOT 263
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#define IMX8MP_CLK_NOC_WRAPPER_ROOT 264
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#define IMX8MP_CLK_VPU_VC8KE_ROOT 265
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#define IMX8MP_CLK_VPU_G2_ROOT 266
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#define IMX8MP_CLK_NPU_ROOT 267
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#define IMX8MP_CLK_HSIO_ROOT 268
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#define IMX8MP_CLK_MEDIA_APB_ROOT 269
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#define IMX8MP_CLK_MEDIA_AXI_ROOT 270
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#define IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT 271
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#define IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT 272
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#define IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT 273
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#define IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT 274
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#define IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT 275
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#define IMX8MP_CLK_MEDIA_ISP_ROOT 276
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#define IMX8MP_CLK_USDHC3_ROOT 277
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#define IMX8MP_CLK_HDMI_ROOT 278
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#define IMX8MP_CLK_XTAL_ROOT 279
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#define IMX8MP_CLK_PLL_ROOT 280
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#define IMX8MP_CLK_TSENSOR_ROOT 281
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#define IMX8MP_CLK_VPU_ROOT 282
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#define IMX8MP_CLK_MRPR_ROOT 283
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#define IMX8MP_CLK_AUDIO_ROOT 284
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#define IMX8MP_CLK_DRAM_ALT_ROOT 285
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#define IMX8MP_CLK_DRAM_CORE 286
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#define IMX8MP_CLK_ARM 287
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#define IMX8MP_CLK_END 288
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#endif
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