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77a318545d
Fixed some broken instances of "#ifdef CMD_CFG_IDE" too. Those always evaluated TRUE, and thus were always compiled even when IDE really wasn't defined/wanted. Signed-off-by: Jon Loeliger <jdl@freescale.com>
265 lines
6.9 KiB
C
265 lines
6.9 KiB
C
/*
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* (C) Copyright 2003-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2004
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* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
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*
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* (C) Copyright 2004
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* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc5xxx.h>
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#include <pci.h>
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#if defined(CONFIG_MPC5200_DDR)
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#include "mt46v16m16-75.h"
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#else
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#include "mt48lc16m16a2-75.h"
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#endif
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#ifndef CFG_RAMBOOT
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static void sdram_start (int hi_addr)
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{
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long hi_addr_bit = hi_addr ? 0x01000000 : 0;
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/* unlock mode register */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
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__asm__ volatile ("sync");
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/* precharge all banks */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
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__asm__ volatile ("sync");
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#if SDRAM_DDR
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/* set mode register: extended mode */
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*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
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__asm__ volatile ("sync");
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/* set mode register: reset DLL */
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*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
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__asm__ volatile ("sync");
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#endif
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/* precharge all banks */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
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__asm__ volatile ("sync");
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/* auto refresh */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
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__asm__ volatile ("sync");
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/* set mode register */
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*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
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__asm__ volatile ("sync");
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/* normal operation */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
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__asm__ volatile ("sync");
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}
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#endif
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/*
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* ATTENTION: Although partially referenced initdram does NOT make real use
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* use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
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* is something else than 0x00000000.
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*/
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long int initdram (int board_type)
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{
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ulong dramsize = 0;
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#ifndef CFG_RAMBOOT
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ulong test1, test2;
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/* setup SDRAM chip selects */
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*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
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*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
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__asm__ volatile ("sync");
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/* setup config registers */
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*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
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*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
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__asm__ volatile ("sync");
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#if SDRAM_DDR
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/* set tap delay */
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*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
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__asm__ volatile ("sync");
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#endif
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/* find RAM size using SDRAM CS0 only */
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sdram_start(0);
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test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
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sdram_start(1);
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test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
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if (test1 > test2) {
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sdram_start(0);
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dramsize = test1;
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} else {
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dramsize = test2;
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}
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/* memory smaller than 1MB is impossible */
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if (dramsize < (1 << 20)) {
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dramsize = 0;
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}
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/* set SDRAM CS0 size according to the amount of RAM found */
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if (dramsize > 0) {
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*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
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__builtin_ffs(dramsize >> 20) - 1;
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} else {
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*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
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}
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*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
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#else /* CFG_RAMBOOT */
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/* retrieve size of memory connected to SDRAM CS0 */
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dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
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if (dramsize >= 0x13) {
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dramsize = (1 << (dramsize - 0x13)) << 20;
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} else {
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dramsize = 0;
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}
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/* retrieve size of memory connected to SDRAM CS1 */
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dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
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if (dramsize2 >= 0x13) {
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dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
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} else {
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dramsize2 = 0;
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}
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#endif /* CFG_RAMBOOT */
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/* return dramsize + dramsize2; */
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return dramsize;
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}
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int checkboard (void)
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{
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puts ("Board: INKA 4X0\n");
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return 0;
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}
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void flash_preinit(void)
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{
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/*
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* Now, when we are in RAM, enable flash write
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* access for detection process.
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* Note that CS_BOOT cannot be cleared when
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* executing in flash.
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*/
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*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
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}
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int misc_init_f (void)
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{
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uchar tmp[10];
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int i, br;
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i = getenv_r("brightness", tmp, sizeof(tmp));
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br = (i > 0)
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? (int) simple_strtoul (tmp, NULL, 10)
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: CFG_BRIGHTNESS;
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if (br > 255)
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br = 255;
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/* Initialize GPIO output pins.
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*/
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/* Configure GPT as GPIO output (and set them as they control low-active LEDs */
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*(vu_long *)MPC5XXX_GPT0_ENABLE =
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*(vu_long *)MPC5XXX_GPT1_ENABLE =
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*(vu_long *)MPC5XXX_GPT2_ENABLE =
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*(vu_long *)MPC5XXX_GPT3_ENABLE =
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*(vu_long *)MPC5XXX_GPT4_ENABLE =
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*(vu_long *)MPC5XXX_GPT5_ENABLE = 0x34;
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/* Configure GPT7 as PWM timer, 1kHz, no ints. */
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*(vu_long *)MPC5XXX_GPT7_ENABLE = 0;/* Disable */
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*(vu_long *)MPC5XXX_GPT7_COUNTER = 0x020000fe;
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*(vu_long *)MPC5XXX_GPT7_PWMCFG = (br << 16);
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*(vu_long *)MPC5XXX_GPT7_ENABLE = 0x3;/* Enable PWM mode and start */
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/* Configure PSC3_6,7 as GPIO output */
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*(vu_long *)MPC5XXX_GPIO_ENABLE |= 0x00003000;
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*(vu_long *)MPC5XXX_GPIO_DIR |= 0x00003000;
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/* Configure PSC3_8 as GPIO output, no interrupt */
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*(vu_long *)MPC5XXX_GPIO_SI_ENABLE |= 0x04000000;
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*(vu_long *)MPC5XXX_GPIO_SI_DIR |= 0x04000000;
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*(vu_long *)MPC5XXX_GPIO_SI_IEN &= ~0x04000000;
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/* Configure PSC3_9 and GPIO_WKUP6,7 as GPIO output */
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*(vu_long *)MPC5XXX_WU_GPIO_ENABLE |= 0xc4000000;
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*(vu_long *)MPC5XXX_WU_GPIO_DIR |= 0xc4000000;
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/* Set LR mirror bit because it is low-active */
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*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WKUP_7;
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/*
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* Reset Coral-P graphics controller
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*/
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*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9;
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*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC3_9;
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*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC3_9;
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return 0;
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}
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#ifdef CONFIG_PCI
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static struct pci_controller hose;
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extern void pci_mpc5xxx_init(struct pci_controller *);
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void pci_init_board(void)
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{
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pci_mpc5xxx_init(&hose);
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}
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#endif
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#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
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void init_ide_reset (void)
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{
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debug ("init_ide_reset\n");
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/* Configure PSC1_4 as GPIO output for ATA reset */
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*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
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*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
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/* Deassert reset */
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*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
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}
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void ide_set_reset (int idereset)
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{
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debug ("ide_reset(%d)\n", idereset);
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if (idereset) {
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*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
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/* Make a delay. MPC5200 spec says 25 usec min */
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udelay(500000);
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} else {
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*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
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}
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}
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#endif
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