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a821c4af79
These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org>
136 lines
3.3 KiB
C
136 lines
3.3 KiB
C
/*
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* (C) Copyright 2017
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* Vikas Manocha, <vikas.manocha@st.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/stm32.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#define MAX_SIZE_BANK_NAME 5
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#define STM32_GPIOS_PER_BANK 16
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#define MODE_BITS(gpio_pin) (gpio_pin * 2)
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#define MODE_BITS_MASK 3
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#define IN_OUT_BIT_INDEX(gpio_pin) (1UL << (gpio_pin))
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DECLARE_GLOBAL_DATA_PTR;
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static int stm32_gpio_direction_input(struct udevice *dev, unsigned offset)
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{
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struct stm32_gpio_priv *priv = dev_get_priv(dev);
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struct stm32_gpio_regs *regs = priv->regs;
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int bits_index = MODE_BITS(offset);
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int mask = MODE_BITS_MASK << bits_index;
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clrsetbits_le32(®s->moder, mask, STM32_GPIO_MODE_IN << bits_index);
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return 0;
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}
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static int stm32_gpio_direction_output(struct udevice *dev, unsigned offset,
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int value)
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{
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struct stm32_gpio_priv *priv = dev_get_priv(dev);
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struct stm32_gpio_regs *regs = priv->regs;
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int bits_index = MODE_BITS(offset);
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int mask = MODE_BITS_MASK << bits_index;
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clrsetbits_le32(®s->moder, mask, STM32_GPIO_MODE_OUT << bits_index);
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mask = IN_OUT_BIT_INDEX(offset);
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clrsetbits_le32(®s->odr, mask, value ? mask : 0);
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return 0;
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}
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static int stm32_gpio_get_value(struct udevice *dev, unsigned offset)
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{
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struct stm32_gpio_priv *priv = dev_get_priv(dev);
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struct stm32_gpio_regs *regs = priv->regs;
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return readl(®s->idr) & IN_OUT_BIT_INDEX(offset) ? 1 : 0;
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}
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static int stm32_gpio_set_value(struct udevice *dev, unsigned offset, int value)
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{
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struct stm32_gpio_priv *priv = dev_get_priv(dev);
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struct stm32_gpio_regs *regs = priv->regs;
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int mask = IN_OUT_BIT_INDEX(offset);
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clrsetbits_le32(®s->odr, mask, value ? mask : 0);
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return 0;
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}
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static const struct dm_gpio_ops gpio_stm32_ops = {
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.direction_input = stm32_gpio_direction_input,
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.direction_output = stm32_gpio_direction_output,
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.get_value = stm32_gpio_get_value,
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.set_value = stm32_gpio_set_value,
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};
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static int gpio_stm32_probe(struct udevice *dev)
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{
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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struct stm32_gpio_priv *priv = dev_get_priv(dev);
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fdt_addr_t addr;
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char *name;
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addr = devfdt_get_addr(dev);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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priv->regs = (struct stm32_gpio_regs *)addr;
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name = (char *)fdtdec_locate_byte_array(gd->fdt_blob,
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dev_of_offset(dev),
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"st,bank-name",
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MAX_SIZE_BANK_NAME);
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if (!name)
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return -EINVAL;
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uc_priv->bank_name = name;
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uc_priv->gpio_count = STM32_GPIOS_PER_BANK;
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debug("%s, addr = 0x%p, bank_name = %s\n", __func__, (u32 *)priv->regs,
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uc_priv->bank_name);
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#ifdef CONFIG_CLK
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struct clk clk;
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int ret;
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ret = clk_get_by_index(dev, 0, &clk);
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if (ret < 0)
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return ret;
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ret = clk_enable(&clk);
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if (ret) {
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dev_err(dev, "failed to enable clock\n");
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return ret;
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}
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debug("clock enabled for device %s\n", dev->name);
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#endif
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return 0;
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}
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static const struct udevice_id stm32_gpio_ids[] = {
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{ .compatible = "st,stm32-gpio" },
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{ }
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};
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U_BOOT_DRIVER(gpio_stm32) = {
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.name = "gpio_stm32",
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.id = UCLASS_GPIO,
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.of_match = stm32_gpio_ids,
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.probe = gpio_stm32_probe,
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.ops = &gpio_stm32_ops,
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.flags = DM_FLAG_PRE_RELOC | DM_UC_FLAG_SEQ_ALIAS,
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.priv_auto_alloc_size = sizeof(struct stm32_gpio_priv),
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};
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