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The current name is inconsistent with SPL which uses CONFIG_SPL_TEXT_BASE and this makes it imposible to use CONFIG_VAL(). Rename it to resolve this problem. Signed-off-by: Simon Glass <sjg@chromium.org>
53 lines
2.1 KiB
Plaintext
53 lines
2.1 KiB
Plaintext
Overview of SPL on OMAP3 devices
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================================
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Introduction
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------------
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This document provides an overview of how SPL functions on OMAP3 (and related
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such as am35x and am37x) processors.
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Methodology
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-----------
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On these platforms the ROM supports trying a sequence of boot devices. Once
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one has been used successfully to load SPL this information is stored in memory
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and the location stored in a register. We will read this to determine where to
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read U-Boot from in turn.
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Memory Map
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----------
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This is an example of a typical setup. See top-level README for documentation
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of which CONFIG variables control these values. For a given board and the
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amount of DRAM available to it different values may need to be used.
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Note that the size of the SPL text rodata and data is enforced with a CONFIG
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option and growing over that size results in a link error. The SPL stack
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starts at the top of SRAM (which is configurable) and grows downward. The
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space between the top of SRAM and the enforced upper bound on the size of the
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SPL text, data and rodata is considered the safe stack area. Details on
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confirming this behavior are shown below.
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A portion of the system memory map looks as follows:
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SRAM: 0x40200000 - 0x4020FFFF
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DDR1: 0x80000000 - 0xBFFFFFFF
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Option 1 (SPL only):
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0x40200800 - 0x4020BBFF: Area for SPL text, data and rodata
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0x4020E000 - 0x4020FFFC: Area for the SPL stack.
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0x80000000 - 0x8007FFFF: Area for the SPL BSS.
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0x80100000: CONFIG_TEXT_BASE of U-Boot
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0x80208000 - 0x80307FFF: malloc() pool available to SPL.
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Option 2 (SPL or X-Loader):
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0x40200800 - 0x4020BBFF: Area for SPL text, data and rodata
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0x4020E000 - 0x4020FFFC: Area for the SPL stack.
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0x80008000: CONFIG_TEXT_BASE of U-Boot
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0x87000000 - 0x8707FFFF: Area for the SPL BSS.
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0x87080000 - 0x870FFFFF: malloc() pool available to SPL.
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For the areas that reside within DDR1 they must not be used prior to s_init()
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completing. Note that CONFIG_TEXT_BASE must be clear of the areas that SPL
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uses while running. This is why we have two versions of the memory map that
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only vary in where the BSS and malloc pool reside.
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