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4bc0104c97
This patch adds support for MediaTek MT7621 SoC. All files are dedicated for u-boot. The default build target is u-boot-mt7621.bin. The specification of this chip: https://www.mediatek.com/products/homenetworking/mt7621 Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
230 lines
6.4 KiB
C
230 lines
6.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2022 MediaTek Inc. All rights reserved.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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#ifndef _MT7621_H_
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#define _MT7621_H_
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#define SYSCTL_BASE 0x1e000000
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#define SYSCTL_SIZE 0x100
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#define TIMER_BASE 0x1e000100
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#define TIMER_SIZE 0x100
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#define RBUS_BASE 0x1e000400
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#define RBUS_SIZE 0x100
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#define GPIO_BASE 0x1e000600
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#define GPIO_SIZE 0x100
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#define DMA_CFG_ARB_BASE 0x1e000800
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#define DMA_CFG_ARB_SIZE 0x100
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#define SPI_BASE 0x1e000b00
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#define SPI_SIZE 0x100
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#define UART1_BASE 0x1e000c00
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#define UART1_SIZE 0x100
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#define UART2_BASE 0x1e000d00
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#define UART2_SIZE 0x100
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#define UART3_BASE 0x1e000e00
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#define UART3_SIZE 0x100
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#define NFI_BASE 0x1e003000
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#define NFI_SIZE 0x800
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#define NFI_ECC_BASE 0x1e003800
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#define NFI_ECC_SIZE 0x800
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#define DRAMC_BASE 0x1e005000
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#define DRAMC_SIZE 0x1000
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#define FE_BASE 0x1e100000
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#define FE_SIZE 0xe000
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#define GMAC_BASE 0x1e110000
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#define GMAC_SIZE 0x8000
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#define SSUSB_BASE 0x1e1c0000
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#define SSUSB_SIZE 0x40000
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/* GIC Base Address */
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#define MIPS_GIC_BASE 0x1fbc0000
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/* CPC Base Address */
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#define MIPS_CPC_BASE 0x1fbf0000
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/* Flash Memory-mapped Base Address */
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#define FLASH_MMAP_BASE 0x1fc00000
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#define TPL_INFO_OFFSET 0x40
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#define TPL_INFO_MAGIC 0x31323637 /* Magic "7621" */
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/* SRAM */
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#define FE_SRAM_BASE1 0x8000
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#define FE_SRAM_BASE2 0xa000
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/* SYSCTL_BASE */
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#define SYSCTL_CHIP_REV_ID_REG 0x0c
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#define CPU_ID 0x20000
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#define PKG_ID 0x10000
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#define VER_ID_S 8
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#define VER_ID_M 0xf00
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#define ECO_ID_S 0
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#define ECO_ID_M 0x0f
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#define SYSCTL_SYSCFG0_REG 0x10
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#define XTAL_MODE_SEL_S 6
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#define XTAL_MODE_SEL_M 0x1c0
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#define DRAM_TYPE 0x10
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#define CHIP_MODE_S 0
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#define CHIP_MODE_M 0x0f
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#define BOOT_SRAM_BASE_REG 0x20
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#define SYSCTL_CLKCFG0_REG 0x2c
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#define CPU_CLK_SEL_S 30
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#define CPU_CLK_SEL_M 0xc0000000
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#define MPLL_CFG_SEL_S 23
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#define MPLL_CFG_SEL_M 0x800000
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#define SYSCTL_RSTCTL_REG 0x34
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#define MCM_RST 0x04
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#define SYS_RST 0x01
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#define SYSCTL_CUR_CLK_STS_REG 0x44
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#define CUR_CPU_FDIV_S 8
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#define CUR_CPU_FDIV_M 0x1f00
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#define CUR_CPU_FFRAC_S 0
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#define CUR_CPU_FFRAC_M 0x1f
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#define SYSCTL_GPIOMODE_REG 0x60
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#define UART2_MODE_S 5
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#define UART2_MODE_M 0x60
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#define UART3_MODE_S 3
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#define UART3_MODE_M 0x18
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#define UART1_MODE 0x02
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/* RBUS_BASE */
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#define RBUS_DYN_CFG0_REG 0x0010
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#define CPU_FDIV_S 8
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#define CPU_FDIV_M 0x1f00
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#define CPU_FFRAC_S 0
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#define CPU_FFRAC_M 0x1f
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/* DMA_CFG_ARB_BASE */
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#define DMA_ROUTE_REG 0x000c
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/* SPI_BASE */
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#define SPI_SPACE_REG 0x003c
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#define FS_SLAVE_SEL_S 12
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#define FS_SLAVE_SEL_M 0x70000
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#define FS_CLK_SEL_S 0
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#define FS_CLK_SEL_M 0xfff
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/* FE_BASE */
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#define FE_RST_GLO_REG 0x0004
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#define FE_PSE_RAM 0x04
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#define FE_PSE_MEM_EN 0x02
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#define FE_PSE_RESET 0x01
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/* SSUSB_BASE */
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#define SSUSB_MAC_CK_CTRL_REG 0x10784
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#define SSUSB_MAC3_SYS_CK_GATE_MASK_TIME_S 16
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#define SSUSB_MAC3_SYS_CK_GATE_MASK_TIME_M 0xff0000
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#define SSUSB_MAC2_SYS_CK_GATE_MASK_TIME_S 8
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#define SSUSB_MAC2_SYS_CK_GATE_MASK_TIME_M 0xff00
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#define SSUSB_MAC3_SYS_CK_GATE_MODE_S 2
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#define SSUSB_MAC3_SYS_CK_GATE_MODE_M 0x0c
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#define SSUSB_MAC2_SYS_CK_GATE_MODE_S 0
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#define SSUSB_MAC2_SYS_CK_GATE_MODE_M 0x03
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#define SSUSB_B2_ROSC_0_REG 0x10a40
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#define SSUSB_RING_OSC_CNTEND_S 23
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#define SSUSB_RING_OSC_CNTEND_M 0xff800000
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#define SSUSB_XTAL_OSC_CNTEND_S 16
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#define SSUSB_XTAL_OSC_CNTEND_M 0x7f0000
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#define SSUSB_RING_BYPASS_DET 0x01
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#define SSUSB_B2_ROSC_1_REG 0x10a44
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#define SSUSB_RING_OSC_FRC_RECAL_S 17
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#define SSUSB_RING_OSC_FRC_RECAL_M 0x60000
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#define SSUSB_RING_OSC_FRC_SEL 0x01
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#define SSUSB_U3PHYA_1_REG 0x10b04
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#define SSUSB_PCIE_CLKDRV_AMP_S 27
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#define SSUSB_PCIE_CLKDRV_AMP_M 0x38000000
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#define SSUSB_SYSPLL_FBSEL_S 2
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#define SSUSB_SYSPLL_FBSEL_M 0x0c
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#define SSUSB_SYSPLL_PREDIV_S 0
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#define SSUSB_SYSPLL_PREDIV_M 0x03
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#define SSUSB_U3PHYA_2_REG 0x10b08
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#define SSUSB_SYSPLL_FBDIV_S 24
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#define SSUSB_SYSPLL_FBDIV_M 0x7f000000
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#define SSUSB_SYSPLL_VCO_DIV_SEL 0x200000
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#define SSUSB_SYSPLL_FPEN 0x2000
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#define SSUSB_SYSPLL_MONCK_EN 0x1000
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#define SSUSB_SYSPLL_VOD_EN 0x200
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#define SSUSB_U3PHYA_3_REG 0x10b10
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#define SSUSB_SYSPLL_PCW_NCPO_S 1
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#define SSUSB_SYSPLL_PCW_NCPO_M 0xfffffffe
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#define SSUSB_U3PHYA_9_REG 0x10b24
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#define SSUSB_PLL_SSC_PRD_S 0
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#define SSUSB_PLL_SSC_PRD_M 0xffff
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#define SSUSB_U3PHYA_11_REG 0x10b2c
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#define SSUSB_EQ_CURSEL 0x1000000
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#define SSUSB_RX_DAC_MUX_S 19
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#define SSUSB_RX_DAC_MUX_M 0xf80000
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#define SSUSB_PCIE_SIGDET_VTH_S 5
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#define SSUSB_PCIE_SIGDET_VTH_M 0x60
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#define SSUSB_PCIE_SIGDET_LPF_S 3
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#define SSUSB_PCIE_SIGDET_LPF_M 0x18
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#define DA_SSUSB_PLL_FBKDIV_REG 0x10c1c
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#define SSUSB_PLL_FBKDIV_PE2H_S 24
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#define SSUSB_PLL_FBKDIV_PE2H_M 0x7f000000
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#define SSUSB_PLL_FBKDIV_PE1D_S 16
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#define SSUSB_PLL_FBKDIV_PE1D_M 0x7f0000
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#define SSUSB_PLL_FBKDIV_PE1H_S 8
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#define SSUSB_PLL_FBKDIV_PE1H_M 0x7f00
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#define SSUSB_PLL_FBKDIV_U3_S 0
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#define SSUSB_PLL_FBKDIV_U3_M 0x7f
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#define DA_SSUSB_U3PHYA_10_REG 0x10c20
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#define SSUSB_PLL_PREDIV_PE1D_S 18
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#define SSUSB_PLL_PREDIV_PE1D_M 0xc0000
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#define SSUSB_PLL_PREDIV_U3_S 8
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#define SSUSB_PLL_PREDIV_U3_M 0x300
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#define SSUSB_PLL_FBKDI_S 0
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#define SSUSB_PLL_FBKDI_M 0x07
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#define DA_SSUSB_PLL_PCW_NCPO_REG 0x10c24
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#define SSUSB_PLL_PCW_NCPO_U3_S 0
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#define SSUSB_PLL_PCW_NCPO_U3_M 0x7fffffff
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#define DA_SSUSB_PLL_SSC_DELTA1_REG 0x10c38
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#define SSUSB_PLL_SSC_DELTA1_PE1H_S 16
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#define SSUSB_PLL_SSC_DELTA1_PE1H_M 0xffff0000
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#define SSUSB_PLL_SSC_DELTA1_U3_S 0
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#define SSUSB_PLL_SSC_DELTA1_U3_M 0xffff
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#define DA_SSUSB_U3PHYA_21_REG 0x10c40
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#define SSUSB_PLL_SSC_DELTA_U3_S 16
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#define SSUSB_PLL_SSC_DELTA_U3_M 0xffff0000
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#define SSUSB_PLL_SSC_DELTA1_PE2D_S 0
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#define SSUSB_PLL_SSC_DELTA1_PE2D_M 0xffff
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/* MT7621 specific CM values */
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/* GCR_REGx_BASE */
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#define GCR_REG0_BASE_VALUE 0x1c000000
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#define GCR_REG1_BASE_VALUE 0x60000000
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#define GCR_REG2_BASE_VALUE 0x1c000000
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#define GCR_REG3_BASE_VALUE 0x1c000000
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/* GCR_REGx_MASK */
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#define GCR_REG0_MASK_VALUE 0x0000fc00 /* 64M Bus */
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#define GCR_REG1_MASK_VALUE 0x0000f000 /* 256M PCI Mem */
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#define GCR_REG2_MASK_VALUE 0x0000fc00 /* unused */
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#define GCR_REG3_MASK_VALUE 0x0000fc00 /* unused */
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#ifndef __ASSEMBLY__
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unsigned long get_xtal_mhz(void);
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#endif
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#endif /* _MT7621_H_ */
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