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5f9a3003be
Drop all duplicate newlines. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
176 lines
5.2 KiB
C
176 lines
5.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2011-2012 Freescale Semiconductor, Inc.
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*/
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#ifndef _ASM_MPC85xx_CONFIG_H_
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#define _ASM_MPC85xx_CONFIG_H_
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/* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
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#include <fsl_ddrc_version.h>
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#if defined(CONFIG_ARCH_MPC8548)
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#define CFG_SYS_FSL_SRIO_MAX_PORTS 1
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#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
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#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
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#define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
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#elif defined(CONFIG_ARCH_P1021)
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#define QE_MURAM_SIZE 0x6000UL
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#define MAX_QE_RISC 1
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#define QE_NUM_OF_SNUM 28
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#elif defined(CONFIG_ARCH_P1023)
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#define CFG_SYS_NUM_FMAN 1
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#define CFG_SYS_NUM_FM1_DTSEC 2
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#define CFG_SYS_QMAN_NUM_PORTALS 3
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#define CFG_SYS_BMAN_NUM_PORTALS 3
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#define CFG_SYS_FM_MURAM_SIZE 0x10000
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/* P1025 is lower end variant of P1021 */
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#elif defined(CONFIG_ARCH_P1025)
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#define QE_MURAM_SIZE 0x6000UL
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#define MAX_QE_RISC 1
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#define QE_NUM_OF_SNUM 28
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#elif defined(CONFIG_ARCH_P2020)
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#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
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#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
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#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
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#define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
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#elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
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#define CFG_SYS_NUM_FMAN 1
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#define CFG_SYS_NUM_FM1_DTSEC 5
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#define CFG_SYS_NUM_FM1_10GEC 1
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#define CFG_SYS_FM_MURAM_SIZE 0x28000
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#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
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#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
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#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
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#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
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#elif defined(CONFIG_ARCH_P3041)
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#define CFG_SYS_NUM_FMAN 1
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#define CFG_SYS_NUM_FM1_DTSEC 5
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#define CFG_SYS_NUM_FM1_10GEC 1
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#define CFG_SYS_FM_MURAM_SIZE 0x28000
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#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
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#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
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#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
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#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
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#elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
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#define CFG_SYS_NUM_FMAN 2
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#define CFG_SYS_NUM_FM1_DTSEC 4
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#define CFG_SYS_NUM_FM2_DTSEC 4
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#define CFG_SYS_NUM_FM1_10GEC 1
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#define CFG_SYS_NUM_FM2_10GEC 1
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#define CFG_SYS_FM_MURAM_SIZE 0x28000
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#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
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#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
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#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
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#define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
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#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
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#elif defined(CONFIG_ARCH_P5040)
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#define CFG_SYS_NUM_FMAN 2
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#define CFG_SYS_NUM_FM1_DTSEC 5
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#define CFG_SYS_NUM_FM1_10GEC 1
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#define CFG_SYS_NUM_FM2_DTSEC 5
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#define CFG_SYS_NUM_FM2_10GEC 1
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#define CFG_SYS_FM_MURAM_SIZE 0x28000
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#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
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#elif defined(CONFIG_ARCH_T4240)
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#ifdef CONFIG_ARCH_T4240
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#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
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#define CFG_SYS_NUM_FM1_DTSEC 8
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#define CFG_SYS_NUM_FM1_10GEC 2
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#define CFG_SYS_NUM_FM2_DTSEC 8
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#define CFG_SYS_NUM_FM2_10GEC 2
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#else
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#define CFG_SYS_NUM_FM1_DTSEC 6
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#define CFG_SYS_NUM_FM1_10GEC 1
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#define CFG_SYS_NUM_FM2_DTSEC 8
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#define CFG_SYS_NUM_FM2_10GEC 1
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#endif
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#define CFG_SYS_FSL_SRDS_3
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#define CFG_SYS_FSL_SRDS_4
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#define CFG_SYS_NUM_FMAN 2
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#define CFG_SYS_PME_CLK 0
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#define CFG_SYS_FM1_CLK 3
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#define CFG_SYS_FM2_CLK 3
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#define CFG_SYS_FM_MURAM_SIZE 0x60000
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#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
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#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
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#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
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#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
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#define CFG_SYS_NUM_FMAN 1
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#define CFG_SYS_FM1_CLK 0
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#define CFG_SYS_FM_MURAM_SIZE 0x60000
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#ifdef CONFIG_ARCH_B4860
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#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
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#define CFG_SYS_NUM_FM1_DTSEC 6
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#define CFG_SYS_NUM_FM1_10GEC 2
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#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
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#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
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#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
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#else
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#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
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#define CFG_SYS_NUM_FM1_DTSEC 4
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#define CFG_SYS_NUM_FM1_10GEC 0
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#endif
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#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
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#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
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#define CFG_SYS_NUM_FMAN 1
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#define CFG_SYS_NUM_FM1_DTSEC 5
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#define CFG_PME_PLAT_CLK_DIV 2
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#define CFG_SYS_PME_CLK CFG_PME_PLAT_CLK_DIV
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#define CFG_FM_PLAT_CLK_DIV 1
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#define CFG_SYS_FM1_CLK CFG_FM_PLAT_CLK_DIV
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#define CFG_SYS_FM_MURAM_SIZE 0x30000
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#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
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#define QE_MURAM_SIZE 0x6000UL
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#define MAX_QE_RISC 1
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#define QE_NUM_OF_SNUM 28
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#elif defined(CONFIG_ARCH_T1024)
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#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
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#define CFG_SYS_NUM_FMAN 1
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#define CFG_SYS_NUM_FM1_DTSEC 4
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#define CFG_SYS_NUM_FM1_10GEC 1
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#define CFG_SYS_FM1_CLK 0
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#define CFG_QBMAN_CLK_DIV 1
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#define CFG_SYS_FM_MURAM_SIZE 0x30000
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#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
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#define QE_MURAM_SIZE 0x6000UL
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#define MAX_QE_RISC 1
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#define QE_NUM_OF_SNUM 28
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#elif defined(CONFIG_ARCH_T2080)
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#define CFG_SYS_NUM_FMAN 1
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#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
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#if defined(CONFIG_ARCH_T2080)
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#define CFG_SYS_NUM_FM1_DTSEC 8
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#define CFG_SYS_NUM_FM1_10GEC 4
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#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
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#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
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#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
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#endif
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#define CFG_PME_PLAT_CLK_DIV 1
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#define CFG_SYS_PME_CLK CFG_PME_PLAT_CLK_DIV
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#define CFG_SYS_FM1_CLK 0
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#define CFG_SYS_FM_MURAM_SIZE 0x28000
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#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
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#elif defined(CONFIG_ARCH_C29X)
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#define CFG_SYS_FSL_SEC_IDX_OFFSET 0x20000
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#endif
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#endif /* _ASM_MPC85xx_CONFIG_H_ */
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