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03de305ec4
As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
89 lines
2.7 KiB
C
89 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* From coreboot src/soc/intel/broadwell/romstage/power_state.c
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*
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* Copyright (C) 2016 Google, Inc.
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*/
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#include <log.h>
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#include <pci.h>
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#include <asm/io.h>
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#include <asm/intel_regs.h>
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#include <asm/arch/iomap.h>
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#include <asm/arch/lpc.h>
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#include <asm/arch/pch.h>
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#include <asm/arch/pm.h>
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/* Return 0, 3, or 5 to indicate the previous sleep state. */
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static int prev_sleep_state(struct chipset_power_state *ps)
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{
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/* Default to S0. */
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int prev_sleep_state = SLEEP_STATE_S0;
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if (ps->pm1_sts & WAK_STS) {
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switch ((ps->pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) {
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case SLP_TYP_S3:
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if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME))
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prev_sleep_state = SLEEP_STATE_S3;
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break;
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case SLP_TYP_S5:
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prev_sleep_state = SLEEP_STATE_S5;
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break;
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}
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/* Clear SLP_TYP. */
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outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);
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}
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if (ps->gen_pmcon3 & (PWR_FLR | SUS_PWR_FLR))
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prev_sleep_state = SLEEP_STATE_S5;
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return prev_sleep_state;
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}
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static void dump_power_state(struct chipset_power_state *ps)
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{
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debug("PM1_STS: %04x\n", ps->pm1_sts);
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debug("PM1_EN: %04x\n", ps->pm1_en);
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debug("PM1_CNT: %08x\n", ps->pm1_cnt);
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debug("TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts);
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debug("GPE0_STS: %08x %08x %08x %08x\n",
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ps->gpe0_sts[0], ps->gpe0_sts[1],
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ps->gpe0_sts[2], ps->gpe0_sts[3]);
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debug("GPE0_EN: %08x %08x %08x %08x\n",
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ps->gpe0_en[0], ps->gpe0_en[1],
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ps->gpe0_en[2], ps->gpe0_en[3]);
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debug("GEN_PMCON: %04x %04x %04x\n",
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ps->gen_pmcon1, ps->gen_pmcon2, ps->gen_pmcon3);
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debug("Previous Sleep State: S%d\n",
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ps->prev_sleep_state);
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}
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/* Fill power state structure from ACPI PM registers */
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void power_state_get(struct udevice *pch_dev, struct chipset_power_state *ps)
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{
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ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
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ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN);
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ps->pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
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ps->tco1_sts = inw(ACPI_BASE_ADDRESS + TCO1_STS);
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ps->tco2_sts = inw(ACPI_BASE_ADDRESS + TCO2_STS);
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ps->gpe0_sts[0] = inl(ACPI_BASE_ADDRESS + GPE0_STS(0));
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ps->gpe0_sts[1] = inl(ACPI_BASE_ADDRESS + GPE0_STS(1));
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ps->gpe0_sts[2] = inl(ACPI_BASE_ADDRESS + GPE0_STS(2));
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ps->gpe0_sts[3] = inl(ACPI_BASE_ADDRESS + GPE0_STS(3));
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ps->gpe0_en[0] = inl(ACPI_BASE_ADDRESS + GPE0_EN(0));
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ps->gpe0_en[1] = inl(ACPI_BASE_ADDRESS + GPE0_EN(1));
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ps->gpe0_en[2] = inl(ACPI_BASE_ADDRESS + GPE0_EN(2));
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ps->gpe0_en[3] = inl(ACPI_BASE_ADDRESS + GPE0_EN(3));
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dm_pci_read_config16(pch_dev, GEN_PMCON_1, &ps->gen_pmcon1);
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dm_pci_read_config16(pch_dev, GEN_PMCON_2, &ps->gen_pmcon2);
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dm_pci_read_config16(pch_dev, GEN_PMCON_3, &ps->gen_pmcon3);
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ps->prev_sleep_state = prev_sleep_state(ps);
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dump_power_state(ps);
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}
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