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	Since the new RevC LX2160A-RDB board has its 10G Aquantia PHYs at different MDIO bus addresses, we must update both the kernel DTS and u-boot's DTS (in case of DM_ETH) in case the board is indeed RevC or newer. Use the newly introduced get_board_rev() function to trigger a fixup of the kernel DTS to properly match the actual PHY addresses. All this is encapsulated in the fdt_fixup_board_phy_revc() function which will be used in the next patch. Use the newly fdt_fixup_board_phy_revc() function introduced to update both kernel's DTS and u-boot's DTS. Signed-off-by: Florin Chiculita <florinlaurentiu.chiculita@nxp.com> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
		
			
				
	
	
		
			77 lines
		
	
	
		
			1.6 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			77 lines
		
	
	
		
			1.6 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /* SPDX-License-Identifier: GPL-2.0+ */
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| /*
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|  * Copyright 2020 NXP
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|  */
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| 
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| #ifndef __LX2160_H
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| #define __LX2160_H
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| 
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| #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
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| /* SYSCLK */
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| #define QIXIS_SYSCLK_100		0x0
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| #define QIXIS_SYSCLK_125		0x1
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| #define QIXIS_SYSCLK_133		0x2
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| 
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| /* DDRCLK */
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| #define QIXIS_DDRCLK_100		0x0
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| #define QIXIS_DDRCLK_125		0x1
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| #define QIXIS_DDRCLK_133		0x2
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| 
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| #define BRDCFG4_EMI1SEL_MASK		0xF8
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| #define BRDCFG4_EMI1SEL_SHIFT		3
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| #define BRDCFG4_EMI2SEL_MASK		0x07
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| #define BRDCFG4_EMI2SEL_SHIFT		0
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| #endif
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| 
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| #define QIXIS_XMAP_SHIFT		5
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| 
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| /* RTC */
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| #define I2C_MUX_CH_RTC			0xB
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| 
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| /* MAC/PHY configuration */
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| #if defined(CONFIG_FSL_MC_ENET)
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| #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
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| #define AQ_PHY_ADDR1			0x00
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| #define AQ_PHY_ADDR2			0x01
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| #define AQ_PHY_ADDR3			0x02
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| #define AQ_PHY_ADDR4			0x03
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| #endif
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| 
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| #ifdef CONFIG_TARGET_LX2160ARDB
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| #define AQR107_PHY_ADDR1		0x04
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| #define AQR107_PHY_ADDR2		0x05
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| #define AQR107_IRQ_MASK			0x0C
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| #endif
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| 
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| #define CORTINA_PHY_ADDR1		0x0
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| #define INPHI_PHY_ADDR1			0x0
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| 
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| #define RGMII_PHY_ADDR1			0x01
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| #define RGMII_PHY_ADDR2			0x02
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| 
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| #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
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| #define INPHI_PHY_ADDR2			0x1
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| #define SGMII_CARD_PORT1_PHY_ADDR	0x1C
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| #define SGMII_CARD_PORT2_PHY_ADDR	0x1D
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| #define SGMII_CARD_PORT3_PHY_ADDR	0x1E
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| #define SGMII_CARD_PORT4_PHY_ADDR	0x1F
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| #endif
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| #endif
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| 
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| #if IS_ENABLED(CONFIG_TARGET_LX2160ARDB)
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| u8 get_board_rev(void);
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| int fdt_fixup_board_phy_revc(void *fdt);
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| #else
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| static inline u8 get_board_rev(void)
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| {
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| 	return 0;
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| }
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| 
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| static inline int fdt_fixup_board_phy_revc(void *fdt)
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| {
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| 	return 0;
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| }
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| #endif
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| 
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| #endif /* __LX2160_H */
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