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add63f94a9
eLBC IP clock is always a constant divisor of platform clock pre-defined per SoC. Clock ratio register (LCRR) used in current implementation governs eLBC IP output cloc. Update sys_info->freq_localbus to represent eLBC input clock with value constant divisor of platform clock. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
134 lines
2.8 KiB
C
134 lines
2.8 KiB
C
/*
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* Copyright 2004 Freescale Semiconductor.
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* Jeff Brown
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* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
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*
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* (C) Copyright 2000-2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <mpc86xx.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* used in some defintiions of CONFIG_SYS_CLK_FREQ */
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extern unsigned long get_board_sys_clk(unsigned long dummy);
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void get_sys_info(sys_info_t *sys_info)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile ccsr_gur_t *gur = &immap->im_gur;
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uint plat_ratio, e600_ratio;
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plat_ratio = (gur->porpllsr) & 0x0000003e;
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plat_ratio >>= 1;
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switch (plat_ratio) {
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case 0x0:
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sys_info->freq_systembus = 16 * CONFIG_SYS_CLK_FREQ;
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break;
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case 0x02:
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case 0x03:
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case 0x04:
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case 0x05:
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case 0x06:
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case 0x08:
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case 0x09:
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case 0x0a:
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case 0x0c:
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case 0x10:
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sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ;
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break;
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default:
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sys_info->freq_systembus = 0;
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break;
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}
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e600_ratio = (gur->porpllsr) & 0x003f0000;
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e600_ratio >>= 16;
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switch (e600_ratio) {
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case 0x10:
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sys_info->freq_processor = 2 * sys_info->freq_systembus;
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break;
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case 0x19:
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sys_info->freq_processor = 5 * sys_info->freq_systembus / 2;
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break;
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case 0x20:
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sys_info->freq_processor = 3 * sys_info->freq_systembus;
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break;
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case 0x39:
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sys_info->freq_processor = 7 * sys_info->freq_systembus / 2;
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break;
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case 0x28:
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sys_info->freq_processor = 4 * sys_info->freq_systembus;
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break;
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case 0x1d:
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sys_info->freq_processor = 9 * sys_info->freq_systembus / 2;
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break;
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default:
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sys_info->freq_processor = e600_ratio +
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sys_info->freq_systembus;
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break;
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}
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sys_info->freq_localbus = sys_info->freq_systembus;
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}
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/*
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* Measure CPU clock speed (core clock GCLK1, GCLK2)
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* (Approx. GCLK frequency in Hz)
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*/
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int get_clocks(void)
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{
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sys_info_t sys_info;
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get_sys_info(&sys_info);
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gd->cpu_clk = sys_info.freq_processor;
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gd->bus_clk = sys_info.freq_systembus;
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gd->arch.lbc_clk = sys_info.freq_localbus;
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/*
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* The base clock for I2C depends on the actual SOC. Unfortunately,
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* there is no pattern that can be used to determine the frequency, so
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* the only choice is to look up the actual SOC number and use the value
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* for that SOC. This information is taken from application note
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* AN2919.
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*/
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#ifdef CONFIG_ARCH_MPC8610
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gd->arch.i2c1_clk = sys_info.freq_systembus;
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#else
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gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
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#endif
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gd->arch.i2c2_clk = gd->arch.i2c1_clk;
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if (gd->cpu_clk != 0)
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return 0;
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else
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return 1;
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}
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/*
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* get_bus_freq
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* Return system bus freq in Hz
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*/
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ulong get_bus_freq(ulong dummy)
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{
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ulong val;
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sys_info_t sys_info;
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get_sys_info(&sys_info);
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val = sys_info.freq_systembus;
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return val;
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}
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