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https://github.com/smaeul/u-boot.git
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7bebc4b04e
* Add Clock control module (CCM) support * iMX7D SoC introduces 3 main clock sysmtem abstraction for clock root frequency generation denominated clock slices. Core clock slice: hihg speed clock for ARM core Bus clock slice: for bus clocks IP clock slice: Peripheral clocks * At system boot ROM enables PLL_ARM, PLL_DDR, PLL_SYS, PLL_ENET In u-boot, we have to: - Configure PFD3- PFD7 for freq we needed in u-boot - Set clock root for peripherals (ip channel) Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
349 lines
6.6 KiB
C
349 lines
6.6 KiB
C
/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc.
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*
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* Author:
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* Peng Fan <Peng.Fan@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_CLOCK_H
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#define _ASM_ARCH_CLOCK_H
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#include <common.h>
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#include <asm/arch/crm_regs.h>
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#ifdef CONFIG_SYS_MX7_HCLK
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#define MXC_HCLK CONFIG_SYS_MX7_HCLK
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#else
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#define MXC_HCLK 24000000
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#endif
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#ifdef CONFIG_SYS_MX7_CLK32
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#define MXC_CLK32 CONFIG_SYS_MX7_CLK32
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#else
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#define MXC_CLK32 32768
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#endif
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/* Mainly for compatible to imx common code. */
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enum mxc_clock {
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MXC_ARM_CLK = 0,
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MXC_AHB_CLK,
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MXC_IPG_CLK,
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MXC_UART_CLK,
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MXC_CSPI_CLK,
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MXC_AXI_CLK,
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MXC_DDR_CLK,
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MXC_ESDHC_CLK,
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MXC_ESDHC2_CLK,
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MXC_ESDHC3_CLK,
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MXC_I2C_CLK,
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};
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/* PLL supported by i.mx7d */
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enum pll_clocks {
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PLL_CORE, /* Core PLL */
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PLL_SYS, /* System PLL*/
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PLL_ENET, /* Enet PLL */
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PLL_AUDIO, /* Audio PLL */
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PLL_VIDEO, /* Video PLL*/
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PLL_DDR, /* Dram PLL */
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PLL_USB, /* USB PLL, fixed at 480MHZ */
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};
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/* clk src for clock root gen */
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enum clk_root_src {
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OSC_24M_CLK,
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PLL_ARM_MAIN_800M_CLK,
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PLL_SYS_MAIN_480M_CLK,
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PLL_SYS_MAIN_240M_CLK,
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PLL_SYS_MAIN_120M_CLK,
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PLL_SYS_PFD0_392M_CLK,
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PLL_SYS_PFD0_196M_CLK,
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PLL_SYS_PFD1_332M_CLK,
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PLL_SYS_PFD1_166M_CLK,
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PLL_SYS_PFD2_270M_CLK,
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PLL_SYS_PFD2_135M_CLK,
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PLL_SYS_PFD3_CLK,
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PLL_SYS_PFD4_CLK,
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PLL_SYS_PFD5_CLK,
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PLL_SYS_PFD6_CLK,
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PLL_SYS_PFD7_CLK,
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PLL_ENET_MAIN_500M_CLK,
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PLL_ENET_MAIN_250M_CLK,
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PLL_ENET_MAIN_125M_CLK,
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PLL_ENET_MAIN_100M_CLK,
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PLL_ENET_MAIN_50M_CLK,
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PLL_ENET_MAIN_40M_CLK,
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PLL_ENET_MAIN_25M_CLK,
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PLL_DRAM_MAIN_1066M_CLK,
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PLL_DRAM_MAIN_533M_CLK,
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PLL_AUDIO_MAIN_CLK,
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PLL_VIDEO_MAIN_CLK,
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PLL_USB_MAIN_480M_CLK, /* fixed at 480MHZ */
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EXT_CLK_1,
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EXT_CLK_2,
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EXT_CLK_3,
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EXT_CLK_4,
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REF_1M_CLK,
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OSC_32K_CLK,
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};
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/*
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* Clock root index
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*/
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enum clk_root_index {
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ARM_A7_CLK_ROOT = 0,
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ARM_M4_CLK_ROOT = 1,
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ARM_M0_CLK_ROOT = 2,
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MAIN_AXI_CLK_ROOT = 16,
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DISP_AXI_CLK_ROOT = 17,
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ENET_AXI_CLK_ROOT = 18,
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NAND_USDHC_BUS_CLK_ROOT = 19,
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AHB_CLK_ROOT = 32,
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DRAM_PHYM_CLK_ROOT = 48,
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DRAM_CLK_ROOT = 49,
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DRAM_PHYM_ALT_CLK_ROOT = 64,
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DRAM_ALT_CLK_ROOT = 65,
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USB_HSIC_CLK_ROOT = 66,
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PCIE_CTRL_CLK_ROOT = 67,
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PCIE_PHY_CLK_ROOT = 68,
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EPDC_PIXEL_CLK_ROOT = 69,
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LCDIF_PIXEL_CLK_ROOT = 70,
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MIPI_DSI_EXTSER_CLK_ROOT = 71,
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MIPI_CSI_WARP_CLK_ROOT = 72,
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MIPI_DPHY_REF_CLK_ROOT = 73,
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SAI1_CLK_ROOT = 74,
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SAI2_CLK_ROOT = 75,
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SAI3_CLK_ROOT = 76,
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SPDIF_CLK_ROOT = 77,
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ENET1_REF_CLK_ROOT = 78,
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ENET1_TIME_CLK_ROOT = 79,
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ENET2_REF_CLK_ROOT = 80,
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ENET2_TIME_CLK_ROOT = 81,
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ENET_PHY_REF_CLK_ROOT = 82,
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EIM_CLK_ROOT = 83,
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NAND_CLK_ROOT = 84,
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QSPI_CLK_ROOT = 85,
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USDHC1_CLK_ROOT = 86,
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USDHC2_CLK_ROOT = 87,
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USDHC3_CLK_ROOT = 88,
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CAN1_CLK_ROOT = 89,
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CAN2_CLK_ROOT = 90,
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I2C1_CLK_ROOT = 91,
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I2C2_CLK_ROOT = 92,
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I2C3_CLK_ROOT = 93,
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I2C4_CLK_ROOT = 94,
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UART1_CLK_ROOT = 95,
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UART2_CLK_ROOT = 96,
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UART3_CLK_ROOT = 97,
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UART4_CLK_ROOT = 98,
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UART5_CLK_ROOT = 99,
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UART6_CLK_ROOT = 100,
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UART7_CLK_ROOT = 101,
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ECSPI1_CLK_ROOT = 102,
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ECSPI2_CLK_ROOT = 103,
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ECSPI3_CLK_ROOT = 104,
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ECSPI4_CLK_ROOT = 105,
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PWM1_CLK_ROOT = 106,
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PWM2_CLK_ROOT = 107,
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PWM3_CLK_ROOT = 108,
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PWM4_CLK_ROOT = 109,
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FLEXTIMER1_CLK_ROOT = 110,
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FLEXTIMER2_CLK_ROOT = 111,
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SIM1_CLK_ROOT = 112,
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SIM2_CLK_ROOT = 113,
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GPT1_CLK_ROOT = 114,
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GPT2_CLK_ROOT = 115,
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GPT3_CLK_ROOT = 116,
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GPT4_CLK_ROOT = 117,
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TRACE_CLK_ROOT = 118,
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WDOG_CLK_ROOT = 119,
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CSI_MCLK_CLK_ROOT = 120,
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AUDIO_MCLK_CLK_ROOT = 121,
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WRCLK_CLK_ROOT = 122,
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IPP_DO_CLKO1 = 123,
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IPP_DO_CLKO2 = 124,
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CLK_ROOT_MAX,
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};
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struct clk_root_setting {
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enum clk_root_index root;
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u32 setting;
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};
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/*
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* CCGR mapping
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*/
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enum clk_ccgr_index {
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CCGR_CPU = 0,
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CCGR_M4 = 1,
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CCGR_SIM_MAIN = 4,
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CCGR_SIM_DISPLAY = 5,
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CCGR_SIM_ENET = 6,
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CCGR_SIM_M = 7,
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CCGR_SIM_S = 8,
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CCGR_SIM_WAKEUP = 9,
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CCGR_IPMUX1 = 10,
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CCGR_IPMUX2 = 11,
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CCGR_IPMUX3 = 12,
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CCGR_ROM = 16,
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CCGR_OCRAM = 17,
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CCGR_OCRAM_S = 18,
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CCGR_DRAM = 19,
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CCGR_RAWNAND = 20,
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CCGR_QSPI = 21,
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CCGR_WEIM = 22,
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CCGR_ADC = 32,
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CCGR_ANATOP = 33,
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CCGR_SCTR = 34,
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CCGR_OCOTP = 35,
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CCGR_CAAM = 36,
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CCGR_SNVS = 37,
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CCGR_RDC = 38,
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CCGR_MU = 39,
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CCGR_HS = 40,
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CCGR_DVFS = 41,
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CCGR_QOS = 42,
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CCGR_QOS_DISPMIX = 43,
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CCGR_QOS_MEGAMIX = 44,
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CCGR_CSU = 45,
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CCGR_DBGMON = 46,
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CCGR_DEBUG = 47,
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CCGR_TRACE = 48,
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CCGR_SEC_DEBUG = 49,
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CCGR_SEMA1 = 64,
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CCGR_SEMA2 = 65,
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CCGR_PERFMON1 = 68,
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CCGR_PERFMON2 = 69,
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CCGR_SDMA = 72,
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CCGR_CSI = 73,
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CCGR_EPDC = 74,
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CCGR_LCDIF = 75,
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CCGR_PXP = 76,
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CCGR_PCIE = 96,
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CCGR_MIPI_CSI = 100,
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CCGR_MIPI_DSI = 101,
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CCGR_MIPI_MEM_PHY = 102,
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CCGR_USB_CTRL = 104,
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CCGR_USB_HSIC = 105,
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CCGR_USB_PHY1 = 106,
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CCGR_USB_PHY2 = 107,
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CCGR_USDHC1 = 108,
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CCGR_USDHC2 = 109,
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CCGR_USDHC3 = 110,
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CCGR_ENET1 = 112,
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CCGR_ENET2 = 113,
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CCGR_CAN1 = 116,
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CCGR_CAN2 = 117,
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CCGR_ECSPI1 = 120,
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CCGR_ECSPI2 = 121,
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CCGR_ECSPI3 = 122,
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CCGR_ECSPI4 = 123,
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CCGR_GPT1 = 124,
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CCGR_GPT2 = 125,
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CCGR_GPT3 = 126,
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CCGR_GPT4 = 127,
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CCGR_FTM1 = 128,
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CCGR_FTM2 = 129,
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CCGR_PWM1 = 132,
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CCGR_PWM2 = 133,
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CCGR_PWM3 = 134,
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CCGR_PWM4 = 135,
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CCGR_I2C1 = 136,
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CCGR_I2C2 = 137,
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CCGR_I2C3 = 138,
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CCGR_I2C4 = 139,
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CCGR_SAI1 = 140,
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CCGR_SAI2 = 141,
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CCGR_SAI3 = 142,
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CCGR_SIM1 = 144,
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CCGR_SIM2 = 145,
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CCGR_UART1 = 148,
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CCGR_UART2 = 149,
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CCGR_UART3 = 150,
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CCGR_UART4 = 151,
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CCGR_UART5 = 152,
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CCGR_UART6 = 153,
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CCGR_UART7 = 154,
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CCGR_WDOG1 = 156,
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CCGR_WDOG2 = 157,
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CCGR_WDOG3 = 158,
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CCGR_WDOG4 = 159,
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CCGR_GPIO1 = 160,
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CCGR_GPIO2 = 161,
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CCGR_GPIO3 = 162,
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CCGR_GPIO4 = 163,
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CCGR_GPIO5 = 164,
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CCGR_GPIO6 = 165,
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CCGR_GPIO7 = 166,
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CCGR_IOMUX = 168,
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CCGR_IOMUX_LPSR = 169,
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CCGR_KPP = 170,
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CCGR_SKIP,
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CCGR_MAX,
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};
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/* Clock root channel */
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enum clk_root_type {
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CCM_CORE_CHANNEL,
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CCM_BUS_CHANNEL,
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CCM_AHB_CHANNEL,
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CCM_DRAM_PHYM_CHANNEL,
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CCM_DRAM_CHANNEL,
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CCM_IP_CHANNEL,
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};
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#include <asm/arch/clock_slice.h>
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/*
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* entry: the clock root index
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* type: ccm channel
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* src_mux: each entry corresponding to the clock src, detailed info in CCM RM
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*/
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struct clk_root_map {
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enum clk_root_index entry;
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enum clk_root_type type;
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uint8_t src_mux[8];
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};
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enum enet_freq {
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ENET_25MHz,
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ENET_50MHz,
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ENET_125MHz,
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};
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u32 get_root_clk(enum clk_root_index clock_id);
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u32 mxc_get_clock(enum mxc_clock clk);
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u32 imx_get_uartclk(void);
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u32 imx_get_fecclk(void);
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void clock_init(void);
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#ifdef CONFIG_SYS_I2C_MXC
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int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
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#endif
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#ifdef CONFIG_FEC_MXC
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int set_clk_enet(enum enet_freq type);
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#endif
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int set_clk_qspi(void);
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int set_clk_nand(void);
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#ifdef CONFIG_MXC_OCOTP
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void enable_ocotp_clk(unsigned char enable);
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#endif
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void enable_usboh3_clk(unsigned char enable);
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#ifdef CONFIG_SECURE_BOOT
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void hab_caam_clock_enable(unsigned char enable);
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#endif
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void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq);
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void enable_thermal_clk(void);
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#endif
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