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377 lines
9.6 KiB
C
377 lines
9.6 KiB
C
/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Changes for MATRIX Vision MVsensor (C) Copyright 2001
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* MATRIX Vision GmbH / hg, info@matrix-vision.de
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc8xx.h>
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/* ------------------------------------------------------------------------- */
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static long int dram_size (long int, long int *, long int);
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/* ------------------------------------------------------------------------- */
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#define _NOT_USED_ 0xFFFFFFFF
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const uint sdram_table[] =
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{
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/*
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* Single Read. (Offset 0 in UPMA RAM)
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*/
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0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,
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0x1FF5FC47, /* last */
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/*
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* SDRAM Initialization (offset 5 in UPMA RAM)
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*
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* This is no UPM entry point. The following definition uses
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* the remaining space to establish an initialization
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* sequence, which is executed by a RUN command.
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*
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*/
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0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
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/*
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* Burst Read. (Offset 8 in UPMA RAM)
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*/
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0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
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0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Single Write. (Offset 18 in UPMA RAM)
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*/
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0x1F0DFC04 /*0x1F2DFC04??*/, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Burst Write. (Offset 20 in UPMA RAM)
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*/
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0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
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0xF0AFFC00, 0xE1BAFC04, 0x1FF5FC47, /* last */
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_NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Refresh (Offset 30 in UPMA RAM)
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*/
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0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
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0xFFFFFC84, 0xFFFFFC07, /* last */
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_NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Exception. (Offset 3c in UPMA RAM)
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*/
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0x7FFFFC07, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_,
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};
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/* ------------------------------------------------------------------------- */
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/*
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* Check Board Identity:
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*/
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int checkboard (void)
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{
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puts ("Board: MATRIX Vision MVsensor\n");
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return 0;
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}
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#ifdef DO_RAM_TEST
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/* ------------------------------------------------------------------------- */
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/*
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* Test SDRAM by writing its address to itself and reading several times
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*/
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#define READ_RUNS 4
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static void test_dram (unsigned long *start, unsigned long *end)
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{
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unsigned long *addr;
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unsigned long value;
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int read_runs, errors, addr_errors;
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printf ("\nChecking SDRAM from %p to %p\n", start, end);
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udelay (1000000);
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for (addr = start; addr < end; addr++)
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*addr = (unsigned long) addr;
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for (addr = start, addr_errors = 0; addr < end; addr++) {
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for (read_runs = READ_RUNS, errors = 0; read_runs > 0; read_runs--) {
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if ((value = *addr) != (unsigned long) addr)
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errors++;
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}
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if (errors > 0) {
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addr_errors++;
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printf ("SDRAM errors (%d) at %p, last read = %ld\n",
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errors, addr, value);
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udelay (10000);
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}
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}
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printf ("SDRAM check finished, total errors = %d\n", addr_errors);
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}
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#endif /* DO_RAM_TEST */
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/* ------------------------------------------------------------------------- */
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long int initdram (int board_type)
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{
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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long int size_b0, size_b1, size8, size9;
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upmconfig (UPMA, (uint *) sdram_table,
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sizeof (sdram_table) / sizeof (uint));
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/*
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* Preliminary prescaler for refresh (depends on number of
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* banks): This value is selected for four cycles every 62.4 us
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* with two SDRAM banks or four cycles every 31.2 us with one
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* bank. It will be adjusted after memory sizing.
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*/
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memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
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memctl->memc_mar = 0x00000088;
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/*
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* Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
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* preliminary addresses - these have to be modified after the
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* SDRAM size has been determined.
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*/
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memctl->memc_or2 = CFG_OR2_PRELIM;
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memctl->memc_br2 = CFG_BR2_PRELIM;
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#if defined (CFG_OR3_PRELIM) && defined (CFG_BR3_PRELIM)
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if (board_type == 0) { /* "L" type boards have only one bank SDRAM */
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memctl->memc_or3 = CFG_OR3_PRELIM;
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memctl->memc_br3 = CFG_BR3_PRELIM;
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}
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#endif
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memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
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udelay (200);
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/* perform SDRAM initializsation sequence */
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memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
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udelay (1);
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memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */
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udelay (1);
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if (board_type == 0) { /* "L" type boards have only one bank SDRAM */
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memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */
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udelay (1);
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memctl->memc_mcr = 0x80006230; /* SDRAM bank 1 - execute twice */
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udelay (1);
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}
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memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
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udelay (1000);
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/*
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* Check Bank 0 Memory Size for re-configuration
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*
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* try 8 column mode
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*/
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size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE2_PRELIM,
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SDRAM_MAX_SIZE);
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udelay (1000);
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/*
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* try 9 column mode
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*/
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size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE2_PRELIM,
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SDRAM_MAX_SIZE);
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if (size8 < size9) { /* leave configuration at 9 columns */
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size_b0 = size9;
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} else { /* back to 8 columns */
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size_b0 = size8;
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memctl->memc_mamr = CFG_MAMR_8COL;
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udelay (500);
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}
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if (board_type == 0) { /* "L" type boards have only one bank SDRAM */
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/*
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* Check Bank 1 Memory Size
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* use current column settings
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* [9 column SDRAM may also be used in 8 column mode,
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* but then only half the real size will be used.]
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*/
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#if defined (SDRAM_BASE3_PRELIM)
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size_b1 =
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dram_size (memctl->memc_mamr, (ulong *) SDRAM_BASE3_PRELIM,
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SDRAM_MAX_SIZE);
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#else
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size_b1 = 0;
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#endif
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} else {
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size_b1 = 0;
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}
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udelay (1000);
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/*
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* Adjust refresh rate depending on SDRAM type, both banks
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* For types > 128 MBit leave it at the current (fast) rate
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*/
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if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
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/* reduce to 15.6 us (62.4 us / quad) */
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memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
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udelay (1000);
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}
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/*
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* Final mapping: map bigger bank first
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*/
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if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */
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memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
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memctl->memc_br3 =
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(CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
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if (size_b0 > 0) {
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/*
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* Position Bank 0 immediately above Bank 1
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*/
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memctl->memc_or2 =
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((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
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memctl->memc_br2 =
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((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
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+ size_b1;
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} else {
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unsigned long reg;
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/*
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* No bank 0
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*
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* invalidate bank
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*/
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memctl->memc_br2 = 0;
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/* adjust refresh rate depending on SDRAM type, one bank */
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reg = memctl->memc_mptpr;
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reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
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memctl->memc_mptpr = reg;
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}
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} else { /* SDRAM Bank 0 is bigger - map first */
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memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
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memctl->memc_br2 =
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(CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
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if (size_b1 > 0) {
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/*
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* Position Bank 1 immediately above Bank 0
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*/
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memctl->memc_or3 =
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((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
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memctl->memc_br3 =
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((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
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+ size_b0;
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} else {
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unsigned long reg;
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/*
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* No bank 1
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*
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* invalidate bank
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*/
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memctl->memc_br3 = 0;
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/* adjust refresh rate depending on SDRAM type, one bank */
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reg = memctl->memc_mptpr;
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reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
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memctl->memc_mptpr = reg;
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}
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}
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udelay (10000);
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#ifdef DO_RAM_TEST
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if (size_b0 > 0)
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test_dram ((unsigned long *) CFG_SDRAM_BASE,
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(unsigned long *) (CFG_SDRAM_BASE + size_b0));
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#endif
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return (size_b0 + size_b1);
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}
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/* ------------------------------------------------------------------------- */
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/*
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* Check memory range for valid RAM. A simple memory test determines
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* the actually available RAM size between addresses `base' and
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* `base + maxsize'. Some (not all) hardware errors are detected:
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* - short between address lines
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* - short between data lines
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*/
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static long int dram_size (long int mamr_value, long int *base,
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long int maxsize)
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{
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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memctl->memc_mamr = mamr_value;
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return (get_ram_size(base, maxsize));
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}
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/* ------------------------------------------------------------------------- */
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u8 *dhcp_vendorex_prep (u8 * e)
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{
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char *ptr;
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/* DHCP vendor-class-identifier = 60 */
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if ((ptr = getenv ("dhcp_vendor-class-identifier"))) {
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*e++ = 60;
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*e++ = strlen (ptr);
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while (*ptr)
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*e++ = *ptr++;
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}
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/* my DHCP_CLIENT_IDENTIFIER = 61 */
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if ((ptr = getenv ("dhcp_client_id"))) {
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*e++ = 61;
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*e++ = strlen (ptr);
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while (*ptr)
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*e++ = *ptr++;
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}
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return e;
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}
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/* ------------------------------------------------------------------------- */
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u8 *dhcp_vendorex_proc (u8 * popt)
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{
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return NULL;
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}
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