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https://github.com/smaeul/u-boot.git
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7fe32b3442
Instead of a special function, send an event after driver model is inited and adjust the boards which use this function. Signed-off-by: Simon Glass <sjg@chromium.org>
146 lines
3.1 KiB
C
146 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018 Google, Inc
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*/
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#include <common.h>
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#include <debug_uart.h>
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#include <dm.h>
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#include <hang.h>
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#include <image.h>
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#include <init.h>
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#include <log.h>
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#include <spl.h>
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#include <asm/cpu.h>
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#include <asm/global_data.h>
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#include <asm/mtrr.h>
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#include <asm/processor.h>
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#include <asm-generic/sections.h>
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DECLARE_GLOBAL_DATA_PTR;
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static int x86_tpl_init(void)
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{
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int ret;
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debug("%s starting\n", __func__);
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ret = x86_cpu_init_tpl();
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if (ret) {
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debug("%s: x86_cpu_init_tpl() failed\n", __func__);
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return ret;
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}
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ret = spl_init();
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if (ret) {
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debug("%s: spl_init() failed\n", __func__);
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return ret;
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}
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ret = arch_cpu_init();
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if (ret) {
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debug("%s: arch_cpu_init() failed\n", __func__);
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return ret;
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}
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preloader_console_init();
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return 0;
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}
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void board_init_f(ulong flags)
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{
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int ret;
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ret = x86_tpl_init();
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if (ret) {
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debug("Error %d\n", ret);
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panic("x86_tpl_init fail");
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}
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/* Uninit CAR and jump to board_init_f_r() */
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board_init_r(gd, 0);
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}
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void board_init_f_r(void)
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{
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/* Not used since we never call board_init_f_r_trampoline() */
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while (1);
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}
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u32 spl_boot_device(void)
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{
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return IS_ENABLED(CONFIG_CHROMEOS_VBOOT) ? BOOT_DEVICE_CROS_VBOOT :
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BOOT_DEVICE_SPI_MMAP;
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}
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int spl_start_uboot(void)
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{
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return 0;
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}
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void spl_board_announce_boot_device(void)
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{
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printf("SPI flash");
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}
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static int spl_board_load_image(struct spl_image_info *spl_image,
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struct spl_boot_device *bootdev)
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{
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spl_image->size = CONFIG_SYS_MONITOR_LEN; /* We don't know SPL size */
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spl_image->entry_point = CONFIG_SPL_TEXT_BASE;
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spl_image->load_addr = CONFIG_SPL_TEXT_BASE;
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spl_image->os = IH_OS_U_BOOT;
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spl_image->name = "U-Boot";
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debug("Loading to %lx\n", spl_image->load_addr);
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return 0;
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}
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SPL_LOAD_IMAGE_METHOD("SPI", 5, BOOT_DEVICE_SPI_MMAP, spl_board_load_image);
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int spl_spi_load_image(void)
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{
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return -EPERM;
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}
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void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
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{
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debug("Jumping to %s at %lx\n", spl_phase_name(spl_next_phase()),
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(ulong)spl_image->entry_point);
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#ifdef DEBUG
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print_buffer(spl_image->entry_point, (void *)spl_image->entry_point, 1,
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0x20, 0);
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#endif
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jump_to_spl(spl_image->entry_point);
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hang();
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}
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void spl_board_init(void)
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{
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preloader_console_init();
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}
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#if !CONFIG_IS_ENABLED(PCI)
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/*
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* This is a fake PCI bus for TPL when it doesn't have proper PCI. It is enough
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* to bind the devices on the PCI bus, some of which have early-regs properties
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* providing fixed BARs. Individual drivers program these BARs themselves so
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* that they can access the devices. The BARs are allocated statically in the
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* device tree.
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*
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* Once SPL is running it enables PCI properly, but does not auto-assign BARs
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* for devices, so the TPL BARs continue to be used. Once U-Boot starts it does
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* the auto allocation (after relocation).
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*/
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#if CONFIG_IS_ENABLED(OF_REAL)
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static const struct udevice_id tpl_fake_pci_ids[] = {
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{ .compatible = "pci-x86" },
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{ }
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};
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#endif
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U_BOOT_DRIVER(pci_x86) = {
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.name = "pci_x86",
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.id = UCLASS_SIMPLE_BUS,
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.of_match = of_match_ptr(tpl_fake_pci_ids),
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DM_PHASE(tpl)
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};
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#endif
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