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Add bcm281xx architecture support code including a clock framework and chip reset. Define register block base addresses for the bcm281xx architecture and create an empty gpio header file required when CONFIG_CMD_GPIO is set. Signed-off-by: Darwin Rambo <drambo@broadcom.com> Reviewed-by: Steve Rae <srae@broadcom.com> Reviewed-by: Tim Kryger <tkryger@linaro.org>
28 lines
637 B
C
28 lines
637 B
C
/*
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* Copyright 2013 Broadcom Corporation.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/sysmap.h>
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#define EN_MASK 0x08000000 /* Enable timer */
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#define SRSTEN_MASK 0x04000000 /* Enable soft reset */
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#define CLKS_SHIFT 20 /* Clock period shift */
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#define LD_SHIFT 0 /* Reload value shift */
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void reset_cpu(ulong ignored)
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{
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/*
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* Set WD enable, RST enable,
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* 3.9 msec clock period (8), reload value (8*3.9ms)
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*/
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u32 reg = EN_MASK + SRSTEN_MASK + (8 << CLKS_SHIFT) + (8 << LD_SHIFT);
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writel(reg, SECWD2_BASE_ADDR);
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while (1)
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; /* loop forever till reset */
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}
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