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https://github.com/smaeul/u-boot.git
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8ff972c6e9
Merge cpu and lib cache code. Flush cache before disabling. Signed-off-by: Michal Simek <monstr@monstr.eu>
91 lines
2.0 KiB
C
91 lines
2.0 KiB
C
/*
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* (C) Copyright 2007 Michal Simek
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*
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* Michal SIMEK <monstr@monstr.eu>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/asm.h>
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int dcache_status (void)
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{
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int i = 0;
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int mask = 0x80;
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__asm__ __volatile__ ("mfs %0,rmsr"::"r" (i):"memory");
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/* i&=0x80 */
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__asm__ __volatile__ ("and %0,%0,%1"::"r" (i), "r" (mask):"memory");
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return i;
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}
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int icache_status (void)
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{
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int i = 0;
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int mask = 0x20;
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__asm__ __volatile__ ("mfs %0,rmsr"::"r" (i):"memory");
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/* i&=0x20 */
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__asm__ __volatile__ ("and %0,%0,%1"::"r" (i), "r" (mask):"memory");
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return i;
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}
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void icache_enable (void) {
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MSRSET(0x20);
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}
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void icache_disable(void) {
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/* we are not generate ICACHE size -> flush whole cache */
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flush_cache(0, 32768);
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MSRCLR(0x20);
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}
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void dcache_enable (void) {
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MSRSET(0x80);
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}
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void dcache_disable(void) {
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#ifdef XILINX_USE_DCACHE
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#ifdef XILINX_DCACHE_BYTE_SIZE
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flush_cache(0, XILINX_DCACHE_BYTE_SIZE);
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#else
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#warning please rebuild BSPs and update configuration
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flush_cache(0, 32768);
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#endif
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#endif
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MSRCLR(0x80);
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}
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void flush_cache (ulong addr, ulong size)
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{
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int i;
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for (i = 0; i < size; i += 4)
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asm volatile (
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#ifdef CONFIG_ICACHE
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"wic %0, r0;"
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#endif
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"nop;"
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#ifdef CONFIG_DCACHE
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"wdc.flush %0, r0;"
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#endif
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"nop;"
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:
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: "r" (addr + i)
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: "memory");
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}
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