mirror of
https://github.com/smaeul/u-boot.git
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8c103c33fb
Now that Linux has accepted these tags, move the device tree files in U-Boot over to use them. Signed-off-by: Simon Glass <sjg@chromium.org>
227 lines
3.3 KiB
Plaintext
227 lines
3.3 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright : STMicroelectronics 2018
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*/
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#include <dt-bindings/clock/stm32mp1-clksrc.h>
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#include "stm32mp15-u-boot.dtsi"
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#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
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/ {
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aliases {
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i2c3 = &i2c4;
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};
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config {
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u-boot,boot-led = "heartbeat";
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u-boot,error-led = "error";
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u-boot,mmc-env-partition = "fip";
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st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
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st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
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};
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#if defined(CONFIG_STM32MP15x_STM32IMAGE) || defined(CONFIG_SPL)
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config {
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u-boot,mmc-env-partition = "ssbl";
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};
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#endif
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#ifdef CONFIG_STM32MP15x_STM32IMAGE
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/* only needed for boot with TF-A, witout FIP support */
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firmware {
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optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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};
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reserved-memory {
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optee@fe000000 {
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reg = <0xfe000000 0x02000000>;
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no-map;
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};
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};
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#endif
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led {
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red {
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label = "error";
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gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
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default-state = "off";
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status = "okay";
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};
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};
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};
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&clk_hse {
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st,digbypass;
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};
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&i2c4 {
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bootph-all;
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};
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&i2c4_pins_a {
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bootph-all;
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pins {
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bootph-all;
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};
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};
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&pmic {
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bootph-all;
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};
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&rcc {
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st,clksrc = <
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CLK_MPU_PLL1P
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CLK_AXI_PLL2P
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CLK_MCU_PLL3P
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CLK_PLL12_HSE
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CLK_PLL3_HSE
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CLK_PLL4_HSE
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CLK_RTC_LSE
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CLK_MCO1_DISABLED
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CLK_MCO2_DISABLED
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>;
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st,clkdiv = <
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1 /*MPU*/
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0 /*AXI*/
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0 /*MCU*/
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1 /*APB1*/
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1 /*APB2*/
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1 /*APB3*/
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1 /*APB4*/
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2 /*APB5*/
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23 /*RTC*/
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0 /*MCO1*/
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0 /*MCO2*/
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>;
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st,pkcs = <
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CLK_CKPER_HSE
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CLK_FMC_ACLK
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CLK_QSPI_ACLK
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CLK_ETH_DISABLED
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CLK_SDMMC12_PLL4P
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CLK_DSI_DSIPLL
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CLK_STGEN_HSE
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CLK_USBPHY_HSE
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CLK_SPI2S1_PLL3Q
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CLK_SPI2S23_PLL3Q
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CLK_SPI45_HSI
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CLK_SPI6_HSI
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CLK_I2C46_HSI
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CLK_SDMMC3_PLL4P
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CLK_USBO_USBPHY
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CLK_ADC_CKPER
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CLK_CEC_LSE
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CLK_I2C12_HSI
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CLK_I2C35_HSI
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CLK_UART1_HSI
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CLK_UART24_HSI
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CLK_UART35_HSI
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CLK_UART6_HSI
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CLK_UART78_HSI
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CLK_SPDIF_PLL4P
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CLK_FDCAN_PLL4R
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CLK_SAI1_PLL3Q
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CLK_SAI2_PLL3Q
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CLK_SAI3_PLL3Q
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CLK_SAI4_PLL3Q
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CLK_RNG1_LSI
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CLK_RNG2_LSI
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CLK_LPTIM1_PCLK1
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CLK_LPTIM23_PCLK3
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CLK_LPTIM45_LSE
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>;
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/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
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pll2: st,pll@1 {
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compatible = "st,stm32mp1-pll";
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reg = <1>;
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cfg = < 2 65 1 0 0 PQR(1,1,1) >;
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frac = < 0x1400 >;
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bootph-all;
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};
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/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
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pll3: st,pll@2 {
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compatible = "st,stm32mp1-pll";
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reg = <2>;
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cfg = < 1 33 1 16 36 PQR(1,1,1) >;
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frac = < 0x1a04 >;
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bootph-all;
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};
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/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
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pll4: st,pll@3 {
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compatible = "st,stm32mp1-pll";
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reg = <3>;
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cfg = < 3 98 5 7 7 PQR(1,1,1) >;
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bootph-all;
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};
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};
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&sdmmc1 {
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bootph-pre-ram;
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};
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&sdmmc1_b4_pins_a {
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bootph-pre-ram;
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pins1 {
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bootph-pre-ram;
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};
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pins2 {
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bootph-pre-ram;
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};
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};
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&sdmmc1_dir_pins_a {
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bootph-pre-ram;
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pins1 {
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bootph-pre-ram;
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};
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pins2 {
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bootph-pre-ram;
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};
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};
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&sdmmc2 {
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bootph-pre-ram;
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};
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&sdmmc2_b4_pins_a {
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bootph-pre-ram;
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pins1 {
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bootph-pre-ram;
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};
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pins2 {
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bootph-pre-ram;
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};
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};
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&sdmmc2_d47_pins_a {
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bootph-pre-ram;
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pins {
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bootph-pre-ram;
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};
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};
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&uart4 {
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bootph-all;
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};
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&uart4_pins_a {
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bootph-all;
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pins1 {
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bootph-all;
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};
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pins2 {
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bootph-all;
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/* pull-up on rx to avoid floating level */
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bias-pull-up;
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};
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};
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