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https://github.com/smaeul/u-boot.git
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7e3d69592b
BCM63148 is an Broadcom B15 based DSL Broadband SoC. It is part of the BCA (Broadband Carrier Access origin) chipset family so it's added under ARCH_BCMBCA platform. This initial support includes a bare-bone implementation and dts with CPU subsystem, memory and Broadcom uart. This SoC is supported in the linux-next git repository so the dts and dtsi files are copied from linux. The u-boot image can be loaded from flash or network to the entry point address in the memory and boot from there. Signed-off-by: William Zhang <william.zhang@broadcom.com>
104 lines
2.2 KiB
Plaintext
104 lines
2.2 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2022 Broadcom Ltd.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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compatible = "brcm,bcm63148", "brcm,bcmbca";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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B15_0: cpu@0 {
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device_type = "cpu";
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compatible = "brcm,brahma-b15";
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reg = <0x0>;
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next-level-cache = <&L2_0>;
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enable-method = "psci";
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};
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B15_1: cpu@1 {
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device_type = "cpu";
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compatible = "brcm,brahma-b15";
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reg = <0x1>;
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next-level-cache = <&L2_0>;
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enable-method = "psci";
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};
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L2_0: l2-cache0 {
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compatible = "cache";
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
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};
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pmu: pmu {
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compatible = "arm,cortex-a15-pmu";
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&B15_0>, <&B15_1>;
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};
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clocks: clocks {
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periph_clk: periph-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <50000000>;
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};
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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axi@80030000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x80030000 0x8000>;
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gic: interrupt-controller@1000 {
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compatible = "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x1000 0x1000>,
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<0x2000 0x2000>,
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<0x4000 0x2000>,
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<0x6000 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_HIGH)>;
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};
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};
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bus@ff800000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0xfffe8000 0x8000>;
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uart0: serial@600 {
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compatible = "brcm,bcm6345-uart";
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reg = <0x600 0x20>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&periph_clk>;
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clock-names = "refclk";
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status = "disabled";
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};
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};
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};
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