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ee71d159aa
Add the secondary cores nodes in the dts file Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com> Cc: Tom Rini <trini@konsulko.com> Cc: Rui Miguel Silva <rui.silva@linaro.org>
77 lines
1.7 KiB
Plaintext
77 lines
1.7 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0 or MIT
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/*
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* Copyright (c) 2022, Arm Limited. All rights reserved.
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* Copyright (c) 2022, Linaro Limited. All rights reserved.
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*
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*/
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/dts-v1/;
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#include "corstone1000.dtsi"
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/ {
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model = "ARM Corstone1000 FVP (Fixed Virtual Platform)";
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compatible = "arm,corstone1000-fvp";
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smsc: ethernet@4010000 {
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compatible = "smsc,lan91c111";
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reg = <0x40100000 0x10000>;
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phy-mode = "mii";
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
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reg-io-width = <2>;
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};
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vmmc_v3_3d: fixed_v3_3d {
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compatible = "regulator-fixed";
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regulator-name = "vmmc_supply";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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sdmmc0: mmc@40300000 {
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compatible = "arm,pl18x", "arm,primecell";
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reg = <0x40300000 0x1000>;
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interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
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max-frequency = <12000000>;
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vmmc-supply = <&vmmc_v3_3d>;
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clocks = <&smbclk>, <&refclk100mhz>;
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clock-names = "smclk", "apb_pclk";
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};
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sdmmc1: mmc@50000000 {
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compatible = "arm,pl18x", "arm,primecell";
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reg = <0x50000000 0x10000>;
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interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
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max-frequency = <12000000>;
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vmmc-supply = <&vmmc_v3_3d>;
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clocks = <&smbclk>, <&refclk100mhz>;
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clock-names = "smclk", "apb_pclk";
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};
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};
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&cpus {
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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reg = <0x1>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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reg = <0x2>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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reg = <0x3>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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};
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};
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