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69060c71dd
Introduce k3-j721e-r5.dtsi to be used by board R5 DTS files. This helps sync SoC changes across boards. Signed-off-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
60 lines
1.1 KiB
Plaintext
60 lines
1.1 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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/dts-v1/;
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#include "k3-j721e-sk.dts"
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#include "k3-j721e-ddr-sk-lp4-4266.dtsi"
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#include "k3-j721e-ddr.dtsi"
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#include "k3-j721e-sk-u-boot.dtsi"
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#include "k3-j721e-r5.dtsi"
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&mcu_uart0_pins_default {
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bootph-pre-ram;
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};
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&wkup_i2c0 {
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bootph-pre-ram;
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tps659412: tps659412@48 {
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reg = <0x48>;
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compatible = "ti,tps659412";
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bootph-pre-ram;
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pinctrl-names = "default";
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pinctrl-0 = <&wkup_i2c0_pins_default>;
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clock-frequency = <400000>;
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regulators: regulators {
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bootph-pre-ram;
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/* 3 Phase Buck */
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buck123_reg: buck123 {
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/* VDD_CPU */
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regulator-name = "buck123";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1250000>;
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regulator-always-on;
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regulator-boot-on;
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bootph-pre-ram;
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};
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};
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esm: esm {
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compatible = "ti,tps659413-esm";
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bootph-pre-ram;
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};
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};
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};
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&wkup_vtm0 {
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vdd-supply-2 = <&buck123_reg>;
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bootph-pre-ram;
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};
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&ospi0 {
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/* Address change for data region (32-bit) */
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reg = <0x0 0x47040000 0x0 0x100>,
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<0x0 0x50000000 0x0 0x8000000>;
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};
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