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	Add clock manager driver for Agilex. Provides clock initialization and get_rate functions. agilex-clock.h is from Linux commit ID cd2e1ad12247. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
		
			
				
	
	
		
			72 lines
		
	
	
		
			2.0 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			72 lines
		
	
	
		
			2.0 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /* SPDX-License-Identifier: GPL-2.0 */
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| /*
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|  * Copyright (C) 2019, Intel Corporation
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|  */
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| 
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| #ifndef __AGILEX_CLOCK_H
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| #define __AGILEX_CLOCK_H
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| 
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| /* fixed rate clocks */
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| #define AGILEX_OSC1			0
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| #define AGILEX_CB_INTOSC_HS_DIV2_CLK	1
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| #define AGILEX_CB_INTOSC_LS_CLK		2
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| #define AGILEX_L4_SYS_FREE_CLK		3
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| #define AGILEX_F2S_FREE_CLK		4
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| 
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| /* PLL clocks */
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| #define AGILEX_MAIN_PLL_CLK		5
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| #define AGILEX_MAIN_PLL_C0_CLK		6
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| #define AGILEX_MAIN_PLL_C1_CLK		7
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| #define AGILEX_MAIN_PLL_C2_CLK		8
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| #define AGILEX_MAIN_PLL_C3_CLK		9
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| #define AGILEX_PERIPH_PLL_CLK		10
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| #define AGILEX_PERIPH_PLL_C0_CLK	11
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| #define AGILEX_PERIPH_PLL_C1_CLK	12
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| #define AGILEX_PERIPH_PLL_C2_CLK	13
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| #define AGILEX_PERIPH_PLL_C3_CLK	14
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| #define AGILEX_MPU_FREE_CLK		15
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| #define AGILEX_MPU_CCU_CLK		16
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| #define AGILEX_BOOT_CLK			17
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| 
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| /* fixed factor clocks */
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| #define AGILEX_L3_MAIN_FREE_CLK		18
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| #define AGILEX_NOC_FREE_CLK		19
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| #define AGILEX_S2F_USR0_CLK		20
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| #define AGILEX_NOC_CLK			21
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| #define AGILEX_EMAC_A_FREE_CLK		22
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| #define AGILEX_EMAC_B_FREE_CLK		23
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| #define AGILEX_EMAC_PTP_FREE_CLK	24
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| #define AGILEX_GPIO_DB_FREE_CLK		25
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| #define AGILEX_SDMMC_FREE_CLK		26
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| #define AGILEX_S2F_USER0_FREE_CLK	27
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| #define AGILEX_S2F_USER1_FREE_CLK	28
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| #define AGILEX_PSI_REF_FREE_CLK		29
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| 
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| /* Gate clocks */
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| #define AGILEX_MPU_CLK			30
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| #define AGILEX_MPU_PERIPH_CLK		31
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| #define AGILEX_L4_MAIN_CLK		32
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| #define AGILEX_L4_MP_CLK		33
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| #define AGILEX_L4_SP_CLK		34
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| #define AGILEX_CS_AT_CLK		35
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| #define AGILEX_CS_TRACE_CLK		36
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| #define AGILEX_CS_PDBG_CLK		37
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| #define AGILEX_CS_TIMER_CLK		38
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| #define AGILEX_S2F_USER0_CLK		39
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| #define AGILEX_EMAC0_CLK		40
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| #define AGILEX_EMAC1_CLK		41
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| #define AGILEX_EMAC2_CLK		42
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| #define AGILEX_EMAC_PTP_CLK		43
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| #define AGILEX_GPIO_DB_CLK		44
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| #define AGILEX_NAND_CLK			45
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| #define AGILEX_PSI_REF_CLK		46
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| #define AGILEX_S2F_USER1_CLK		47
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| #define AGILEX_SDMMC_CLK		48
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| #define AGILEX_SPI_M_CLK		49
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| #define AGILEX_USB_CLK			50
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| #define AGILEX_NAND_X_CLK		51
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| #define AGILEX_NAND_ECC_CLK		52
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| #define AGILEX_NUM_CLKS			53
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| 
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| #endif	/* __AGILEX_CLOCK_H */
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