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9a12e304dd
The clock id needs to be changed to be consistent with Linux. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Reviewed-by: Torsten Duwe <duwe@suse.de> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
259 lines
9.1 KiB
C
259 lines
9.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2022 StarFive Technology Co., Ltd.
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*
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* Author: Yanhong Wang <yanhong.wang@starfivetech.com>
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*/
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#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__
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#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__
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#define JH7110_SYSCLK_PLL0_OUT 0
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#define JH7110_SYSCLK_PLL1_OUT 1
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#define JH7110_SYSCLK_PLL2_OUT 2
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#define JH7110_PLLCLK_END 3
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#define JH7110_SYSCLK_CPU_ROOT 0
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#define JH7110_SYSCLK_CPU_CORE 1
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#define JH7110_SYSCLK_CPU_BUS 2
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#define JH7110_SYSCLK_GPU_ROOT 3
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#define JH7110_SYSCLK_PERH_ROOT 4
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#define JH7110_SYSCLK_BUS_ROOT 5
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#define JH7110_SYSCLK_NOCSTG_BUS 6
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#define JH7110_SYSCLK_AXI_CFG0 7
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#define JH7110_SYSCLK_STG_AXIAHB 8
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#define JH7110_SYSCLK_AHB0 9
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#define JH7110_SYSCLK_AHB1 10
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#define JH7110_SYSCLK_APB_BUS 11
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#define JH7110_SYSCLK_APB0 12
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#define JH7110_SYSCLK_PLL0_DIV2 13
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#define JH7110_SYSCLK_PLL1_DIV2 14
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#define JH7110_SYSCLK_PLL2_DIV2 15
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#define JH7110_SYSCLK_AUDIO_ROOT 16
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#define JH7110_SYSCLK_MCLK_INNER 17
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#define JH7110_SYSCLK_MCLK 18
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#define JH7110_SYSCLK_MCLK_OUT 19
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#define JH7110_SYSCLK_ISP_2X 20
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#define JH7110_SYSCLK_ISP_AXI 21
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#define JH7110_SYSCLK_GCLK0 22
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#define JH7110_SYSCLK_GCLK1 23
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#define JH7110_SYSCLK_GCLK2 24
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#define JH7110_SYSCLK_CORE 25
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#define JH7110_SYSCLK_CORE1 26
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#define JH7110_SYSCLK_CORE2 27
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#define JH7110_SYSCLK_CORE3 28
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#define JH7110_SYSCLK_CORE4 29
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#define JH7110_SYSCLK_DEBUG 30
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#define JH7110_SYSCLK_RTC_TOGGLE 31
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#define JH7110_SYSCLK_TRACE0 32
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#define JH7110_SYSCLK_TRACE1 33
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#define JH7110_SYSCLK_TRACE2 34
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#define JH7110_SYSCLK_TRACE3 35
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#define JH7110_SYSCLK_TRACE4 36
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#define JH7110_SYSCLK_TRACE_COM 37
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#define JH7110_SYSCLK_NOC_BUS_CPU_AXI 38
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#define JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI 39
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#define JH7110_SYSCLK_OSC_DIV2 40
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#define JH7110_SYSCLK_PLL1_DIV4 41
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#define JH7110_SYSCLK_PLL1_DIV8 42
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#define JH7110_SYSCLK_DDR_BUS 43
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#define JH7110_SYSCLK_DDR_AXI 44
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#define JH7110_SYSCLK_GPU_CORE 45
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#define JH7110_SYSCLK_GPU_CORE_CLK 46
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#define JH7110_SYSCLK_GPU_SYS_CLK 47
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#define JH7110_SYSCLK_GPU_APB 48
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#define JH7110_SYSCLK_GPU_RTC_TOGGLE 49
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#define JH7110_SYSCLK_NOC_BUS_GPU_AXI 50
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#define JH7110_SYSCLK_ISP_TOP_CLK_ISPCORE_2X 51
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#define JH7110_SYSCLK_ISP_TOP_CLK_ISP_AXI 52
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#define JH7110_SYSCLK_NOC_BUS_ISP_AXI 53
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#define JH7110_SYSCLK_HIFI4_CORE 54
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#define JH7110_SYSCLK_HIFI4_AXI 55
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#define JH7110_SYSCLK_AXI_CFG1_DEC_MAIN 56
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#define JH7110_SYSCLK_AXI_CFG1_DEC_AHB 57
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#define JH7110_SYSCLK_VOUT_SRC 58
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#define JH7110_SYSCLK_VOUT_AXI 59
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#define JH7110_SYSCLK_NOC_BUS_DISP_AXI 60
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#define JH7110_SYSCLK_VOUT_TOP_CLK_VOUT_AHB 61
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#define JH7110_SYSCLK_VOUT_TOP_CLK_VOUT_AXI 62
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#define JH7110_SYSCLK_VOUT_TOP_CLK_HDMITX0_MCLK 63
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#define JH7110_SYSCLK_VOUT_TOP_CLK_MIPIPHY_REF 64
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#define JH7110_SYSCLK_JPEGC_AXI 65
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#define JH7110_SYSCLK_CODAJ12_AXI 66
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#define JH7110_SYSCLK_CODAJ12_CORE 67
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#define JH7110_SYSCLK_CODAJ12_APB 68
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#define JH7110_SYSCLK_VDEC_AXI 69
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#define JH7110_SYSCLK_WAVE511_AXI 70
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#define JH7110_SYSCLK_WAVE511_BPU 71
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#define JH7110_SYSCLK_WAVE511_VCE 72
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#define JH7110_SYSCLK_WAVE511_APB 73
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#define JH7110_SYSCLK_VDEC_JPG_ARB_JPG 74
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#define JH7110_SYSCLK_VDEC_JPG_ARB_MAIN 75
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#define JH7110_SYSCLK_NOC_BUS_VDEC_AXI 76
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#define JH7110_SYSCLK_VENC_AXI 77
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#define JH7110_SYSCLK_WAVE420L_AXI 78
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#define JH7110_SYSCLK_WAVE420L_BPU 79
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#define JH7110_SYSCLK_WAVE420L_VCE 80
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#define JH7110_SYSCLK_WAVE420L_APB 81
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#define JH7110_SYSCLK_NOC_BUS_VENC_AXI 82
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#define JH7110_SYSCLK_AXI_CFG0_DEC_MAIN_DIV 83
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#define JH7110_SYSCLK_AXI_CFG0_DEC_MAIN 84
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#define JH7110_SYSCLK_AXI_CFG0_DEC_HIFI4 85
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#define JH7110_SYSCLK_AXIMEM2_AXI 86
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#define JH7110_SYSCLK_QSPI_AHB 87
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#define JH7110_SYSCLK_QSPI_APB 88
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#define JH7110_SYSCLK_QSPI_REF_SRC 89
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#define JH7110_SYSCLK_QSPI_REF 90
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#define JH7110_SYSCLK_SDIO0_AHB 91
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#define JH7110_SYSCLK_SDIO1_AHB 92
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#define JH7110_SYSCLK_SDIO0_SDCARD 93
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#define JH7110_SYSCLK_SDIO1_SDCARD 94
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#define JH7110_SYSCLK_USB_125M 95
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#define JH7110_SYSCLK_NOC_BUS_STG_AXI 96
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#define JH7110_SYSCLK_GMAC1_AHB 97
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#define JH7110_SYSCLK_GMAC1_AXI 98
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#define JH7110_SYSCLK_GMAC_SRC 99
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#define JH7110_SYSCLK_GMAC1_GTXCLK 100
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#define JH7110_SYSCLK_GMAC1_RMII_RTX 101
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#define JH7110_SYSCLK_GMAC1_PTP 102
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#define JH7110_SYSCLK_GMAC1_RX 103
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#define JH7110_SYSCLK_GMAC1_RX_INV 104
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#define JH7110_SYSCLK_GMAC1_TX 105
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#define JH7110_SYSCLK_GMAC1_TX_INV 106
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#define JH7110_SYSCLK_GMAC1_GTXC 107
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#define JH7110_SYSCLK_GMAC0_GTXCLK 108
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#define JH7110_SYSCLK_GMAC0_PTP 109
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#define JH7110_SYSCLK_GMAC_PHY 110
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#define JH7110_SYSCLK_GMAC0_GTXC 111
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#define JH7110_SYSCLK_IOMUX_APB 112
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#define JH7110_SYSCLK_MAILBOX 113
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#define JH7110_SYSCLK_INT_CTRL_APB 114
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#define JH7110_SYSCLK_CAN0_APB 115
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#define JH7110_SYSCLK_CAN0_TIMER 116
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#define JH7110_SYSCLK_CAN0_CAN 117
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#define JH7110_SYSCLK_CAN1_APB 118
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#define JH7110_SYSCLK_CAN1_TIMER 119
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#define JH7110_SYSCLK_CAN1_CAN 120
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#define JH7110_SYSCLK_PWM_APB 121
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#define JH7110_SYSCLK_WDT_APB 122
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#define JH7110_SYSCLK_WDT_CORE 123
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#define JH7110_SYSCLK_TIMER_APB 124
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#define JH7110_SYSCLK_TIMER0 125
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#define JH7110_SYSCLK_TIMER1 126
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#define JH7110_SYSCLK_TIMER2 127
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#define JH7110_SYSCLK_TIMER3 128
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#define JH7110_SYSCLK_TEMP_APB 129
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#define JH7110_SYSCLK_TEMP_CORE 130
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#define JH7110_SYSCLK_SPI0_APB 131
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#define JH7110_SYSCLK_SPI1_APB 132
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#define JH7110_SYSCLK_SPI2_APB 133
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#define JH7110_SYSCLK_SPI3_APB 134
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#define JH7110_SYSCLK_SPI4_APB 135
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#define JH7110_SYSCLK_SPI5_APB 136
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#define JH7110_SYSCLK_SPI6_APB 137
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#define JH7110_SYSCLK_I2C0_APB 138
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#define JH7110_SYSCLK_I2C1_APB 139
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#define JH7110_SYSCLK_I2C2_APB 140
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#define JH7110_SYSCLK_I2C3_APB 141
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#define JH7110_SYSCLK_I2C4_APB 142
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#define JH7110_SYSCLK_I2C5_APB 143
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#define JH7110_SYSCLK_I2C6_APB 144
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#define JH7110_SYSCLK_UART0_APB 145
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#define JH7110_SYSCLK_UART0_CORE 146
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#define JH7110_SYSCLK_UART1_APB 147
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#define JH7110_SYSCLK_UART1_CORE 148
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#define JH7110_SYSCLK_UART2_APB 149
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#define JH7110_SYSCLK_UART2_CORE 150
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#define JH7110_SYSCLK_UART3_APB 151
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#define JH7110_SYSCLK_UART3_CORE 152
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#define JH7110_SYSCLK_UART4_APB 153
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#define JH7110_SYSCLK_UART4_CORE 154
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#define JH7110_SYSCLK_UART5_APB 155
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#define JH7110_SYSCLK_UART5_CORE 156
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#define JH7110_SYSCLK_PWMDAC_APB 157
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#define JH7110_SYSCLK_PWMDAC_CORE 158
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#define JH7110_SYSCLK_SPDIF_APB 159
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#define JH7110_SYSCLK_SPDIF_CORE 160
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#define JH7110_SYSCLK_I2STX0_APB 161
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#define JH7110_SYSCLK_I2STX0_BCLK_MST 162
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#define JH7110_SYSCLK_I2STX0_BCLK_MST_INV 163
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#define JH7110_SYSCLK_I2STX0_LRCK_MST 164
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#define JH7110_SYSCLK_I2STX0_BCLK 165
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#define JH7110_SYSCLK_I2STX0_BCLK_INV 166
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#define JH7110_SYSCLK_I2STX0_LRCK 167
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#define JH7110_SYSCLK_I2STX1_APB 168
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#define JH7110_SYSCLK_I2STX1_BCLK_MST 169
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#define JH7110_SYSCLK_I2STX1_BCLK_MST_INV 170
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#define JH7110_SYSCLK_I2STX1_LRCK_MST 171
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#define JH7110_SYSCLK_I2STX1_BCLK 172
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#define JH7110_SYSCLK_I2STX1_BCLK_INV 173
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#define JH7110_SYSCLK_I2STX1_LRCK 174
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#define JH7110_SYSCLK_I2SRX_APB 175
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#define JH7110_SYSCLK_I2SRX_BCLK_MST 176
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#define JH7110_SYSCLK_I2SRX_BCLK_MST_INV 177
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#define JH7110_SYSCLK_I2SRX_LRCK_MST 178
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#define JH7110_SYSCLK_I2SRX_BCLK 179
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#define JH7110_SYSCLK_I2SRX_BCLK_INV 180
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#define JH7110_SYSCLK_I2SRX_LRCK 181
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#define JH7110_SYSCLK_PDM_DMIC 182
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#define JH7110_SYSCLK_PDM_APB 183
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#define JH7110_SYSCLK_TDM_AHB 184
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#define JH7110_SYSCLK_TDM_APB 185
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#define JH7110_SYSCLK_TDM_INTERNAL 186
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#define JH7110_SYSCLK_TDM_CLK_TDM 187
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#define JH7110_SYSCLK_TDM_CLK_TDM_N 188
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#define JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG 189
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#define JH7110_SYSCLK_END 190
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#define JH7110_AONCLK_OSC_DIV4 0
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#define JH7110_AONCLK_APB_FUNC 1
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#define JH7110_AONCLK_GMAC0_AHB 2
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#define JH7110_AONCLK_GMAC0_AXI 3
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#define JH7110_AONCLK_GMAC0_RMII_RTX 4
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#define JH7110_AONCLK_GMAC0_TX 5
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#define JH7110_AONCLK_GMAC0_TX_INV 6
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#define JH7110_AONCLK_GMAC0_RX 7
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#define JH7110_AONCLK_GMAC0_RX_INV 8
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#define JH7110_AONCLK_OTPC_APB 9
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#define JH7110_AONCLK_RTC_APB 10
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#define JH7110_AONCLK_RTC_INTERNAL 11
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#define JH7110_AONCLK_RTC_32K 12
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#define JH7110_AONCLK_RTC_CAL 13
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#define JH7110_AONCLK_END 14
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#define JH7110_STGCLK_HIFI4_CORE 0
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#define JH7110_STGCLK_USB_APB 1
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#define JH7110_STGCLK_USB_UTMI_APB 2
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#define JH7110_STGCLK_USB_AXI 3
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#define JH7110_STGCLK_USB_LPM 4
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#define JH7110_STGCLK_USB_STB 5
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#define JH7110_STGCLK_USB_APP_125 6
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#define JH7110_STGCLK_USB_REFCLK 7
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#define JH7110_STGCLK_PCIE0_AXI 8
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#define JH7110_STGCLK_PCIE0_APB 9
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#define JH7110_STGCLK_PCIE0_TL 10
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#define JH7110_STGCLK_PCIE1_AXI 11
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#define JH7110_STGCLK_PCIE1_APB 12
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#define JH7110_STGCLK_PCIE1_TL 13
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#define JH7110_STGCLK_PCIE01_MAIN 14
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#define JH7110_STGCLK_SEC_HCLK 15
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#define JH7110_STGCLK_SEC_MISCAHB 16
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#define JH7110_STGCLK_MTRX_GRP0_MAIN 17
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#define JH7110_STGCLK_MTRX_GRP0_BUS 18
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#define JH7110_STGCLK_MTRX_GRP0_STG 19
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#define JH7110_STGCLK_MTRX_GRP1_MAIN 20
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#define JH7110_STGCLK_MTRX_GRP1_BUS 21
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#define JH7110_STGCLK_MTRX_GRP1_STG 22
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#define JH7110_STGCLK_MTRX_GRP1_HIFI 23
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#define JH7110_STGCLK_E2_RTC 24
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#define JH7110_STGCLK_E2_CORE 25
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#define JH7110_STGCLK_E2_DBG 26
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#define JH7110_STGCLK_DMA1P_AXI 27
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#define JH7110_STGCLK_DMA1P_AHB 28
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#define JH7110_STGCLK_END 29
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#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ */
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