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adcc90b401
This patch enables embedded flash for stm32f746 discovery board. Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
70 lines
2.0 KiB
C
70 lines
2.0 KiB
C
/*
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* (C) Copyright 2016
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* Vikas Manocha, STMicroelectronics, <vikas.manocha@st.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_HARDWARE_H
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#define _ASM_ARCH_HARDWARE_H
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/* STM32F746 */
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#define ITCM_FLASH_BASE 0x00200000UL
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#define AXIM_FLASH_BASE 0x08000000UL
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#define ITCM_SRAM_BASE 0x00000000UL
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#define DTCM_SRAM_BASE 0x20000000UL
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#define SRAM1_BASE 0x20010000UL
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#define SRAM2_BASE 0x2004C000UL
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#define PERIPH_BASE 0x40000000UL
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#define APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000)
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#define APB2_PERIPH_BASE (PERIPH_BASE + 0x00010000)
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#define AHB1_PERIPH_BASE (PERIPH_BASE + 0x00020000)
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#define AHB2_PERIPH_BASE (PERIPH_BASE + 0x10000000)
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#define AHB3_PERIPH_BASE (PERIPH_BASE + 0x20000000)
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#define TIM2_BASE (APB1_PERIPH_BASE + 0x0000)
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#define USART2_BASE (APB1_PERIPH_BASE + 0x4400)
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#define USART3_BASE (APB1_PERIPH_BASE + 0x4800)
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#define PWR_BASE (APB1_PERIPH_BASE + 0x7000)
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#define USART1_BASE (APB2_PERIPH_BASE + 0x1000)
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#define USART6_BASE (APB2_PERIPH_BASE + 0x1400)
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#define STM32_GPIOA_BASE (AHB1_PERIPH_BASE + 0x0000)
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#define STM32_GPIOB_BASE (AHB1_PERIPH_BASE + 0x0400)
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#define STM32_GPIOC_BASE (AHB1_PERIPH_BASE + 0x0800)
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#define STM32_GPIOD_BASE (AHB1_PERIPH_BASE + 0x0C00)
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#define STM32_GPIOE_BASE (AHB1_PERIPH_BASE + 0x1000)
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#define STM32_GPIOF_BASE (AHB1_PERIPH_BASE + 0x1400)
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#define STM32_GPIOG_BASE (AHB1_PERIPH_BASE + 0x1800)
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#define STM32_GPIOH_BASE (AHB1_PERIPH_BASE + 0x1C00)
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#define STM32_GPIOI_BASE (AHB1_PERIPH_BASE + 0x2000)
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#define STM32_GPIOJ_BASE (AHB1_PERIPH_BASE + 0x2400)
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#define STM32_GPIOK_BASE (AHB1_PERIPH_BASE + 0x2800)
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#define RCC_BASE (AHB1_PERIPH_BASE + 0x3800)
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#define FLASH_CNTL_BASE (AHB1_PERIPH_BASE + 0x3C00)
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#define SDRAM_FMC_BASE (AHB3_PERIPH_BASE + 0x4A0000140)
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static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
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[0 ... 3] = 32 * 1024,
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[4] = 128 * 1024,
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[5 ... 7] = 256 * 1024
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};
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enum clock {
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CLOCK_CORE,
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CLOCK_AHB,
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CLOCK_APB1,
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CLOCK_APB2
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};
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#define STM32_BUS_MASK 0xFFFF0000
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int configure_clocks(void);
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#endif /* _ASM_ARCH_HARDWARE_H */
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