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9c7dea602e
PIRQ routing is pretty much common in Intel chipset. It has several PIRQ links (normally 8) and corresponding registers (either in PCI configuration space or memory-mapped IBASE) to configure the legacy 8259 IRQ vector mapping. Refactor current Queensbay PIRQ routing support using device tree and move it to a common place, so that we can easily add PIRQ routing support on a new platform. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
32 lines
566 B
C
32 lines
566 B
C
/*
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* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _DT_BINDINGS_INTEL_IRQ_H_
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#define _DT_BINDINGS_INTEL_IRQ_H_
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/* PCI interrupt pin */
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#define INTA 1
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#define INTB 2
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#define INTC 3
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#define INTD 4
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/* PIRQs */
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#define PIRQA 0
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#define PIRQB 1
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#define PIRQC 2
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#define PIRQD 3
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#define PIRQE 4
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#define PIRQF 5
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#define PIRQG 6
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#define PIRQH 7
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/* PCI bdf encoding */
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#ifndef PCI_BDF
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#define PCI_BDF(b, d, f) ((b) << 16 | (d) << 11 | (f) << 8)
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#endif
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#endif /* _DT_BINDINGS_INTEL_IRQ_H_ */
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