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03de305ec4
As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
55 lines
1.4 KiB
C
55 lines
1.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2010,2011
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* NVIDIA Corporation <www.nvidia.com>
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*/
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#include <asm/io.h>
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#include <asm/mach-types.h>
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#include <asm/arch/tegra.h>
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#include <asm/arch-tegra/board.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/funcmux.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/pinmux.h>
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#include <asm/gpio.h>
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/* TODO: Remove this code when the SPI switch is working */
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#ifndef CONFIG_TARGET_VENTANA
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void gpio_early_init_uart(void)
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{
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/* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */
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gpio_request(TEGRA_GPIO(I, 3), "uart_en");
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gpio_direction_output(TEGRA_GPIO(I, 3), 0);
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}
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#endif
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#ifdef CONFIG_MMC_SDHCI_TEGRA
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/*
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* Routine: pin_mux_mmc
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* Description: setup the pin muxes/tristate values for the SDMMC(s)
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*/
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void pin_mux_mmc(void)
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{
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funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT);
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funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_4BIT);
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/* For power GPIO PI6 */
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pinmux_tristate_disable(PMUX_PINGRP_ATA);
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/* For CD GPIO PI5 */
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pinmux_tristate_disable(PMUX_PINGRP_ATC);
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}
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#endif
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void pin_mux_usb(void)
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{
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/* For USB0's GPIO PD0. For now, since we have no pinmux in fdt */
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pinmux_tristate_disable(PMUX_PINGRP_SLXK);
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/* For USB1's ULPI signals */
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funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI);
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pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
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pinmux_tristate_disable(PMUX_PINGRP_CDEV2);
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/* USB1 PHY reset GPIO */
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pinmux_tristate_disable(PMUX_PINGRP_UAC);
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}
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