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b0b08ce0b7
An earlier conversion from struct to defines introduced two errors, both
related to setup of EMAC routed via the FPGA. One of the offsets was
incorrect, and the EMAC0/EMAC1 were swapped.
The effect of this was rather odd: both ports could operate at gigabit,
but one of them would fail to transmit when operating at 100Mbit.
Fixes: db5741f7a85ec3ee79b64496172afaa7dc2cb225 ("arm: socfpga: Convert system manager from struct to defines")
Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
45 lines
1.3 KiB
C
45 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
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*/
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#ifndef _SYSTEM_MANAGER_GEN5_H_
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#define _SYSTEM_MANAGER_GEN5_H_
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#ifndef __ASSEMBLY__
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void sysmgr_pinmux_init(void);
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void sysmgr_config_warmrstcfgio(int enable);
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void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len);
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#define SYSMGR_GEN5_WDDBG 0x10
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#define SYSMGR_GEN5_BOOTINFO 0x14
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#define SYSMGR_GEN5_FPGAINFGRP_GBL 0x20
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#define SYSMGR_GEN5_FPGAINFGRP_INDIV 0x24
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#define SYSMGR_GEN5_FPGAINFGRP_MODULE 0x28
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#define SYSMGR_GEN5_SCANMGRGRP_CTRL 0x30
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#define SYSMGR_GEN5_ISWGRP_HANDOFF 0x80
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#define SYSMGR_GEN5_ROMCODEGRP_CTRL 0xc0
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#define SYSMGR_GEN5_WARMRAMGRP_EN 0xe0
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#define SYSMGR_GEN5_SDMMC 0x108
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#define SYSMGR_GEN5_ECCGRP_OCRAM 0x144
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#define SYSMGR_GEN5_EMACIO 0x400
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#define SYSMGR_GEN5_NAND_USEFPGA 0x6f0
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#define SYSMGR_GEN5_RGMII1_USEFPGA 0x6f8
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#define SYSMGR_GEN5_SDMMC_USEFPGA 0x708
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#define SYSMGR_GEN5_RGMII0_USEFPGA 0x714
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#define SYSMGR_GEN5_SPIM1_USEFPGA 0x730
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#define SYSMGR_GEN5_SPIM0_USEFPGA 0x738
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#define SYSMGR_SDMMC SYSMGR_GEN5_SDMMC
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#define SYSMGR_ISWGRP_HANDOFF_OFFSET(i) \
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SYSMGR_GEN5_ISWGRP_HANDOFF + ((i) * sizeof(u32))
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#endif
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#define SYSMGR_SDMMC_SMPLSEL_SHIFT 3
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#define SYSMGR_BOOTINFO_BSEL_SHIFT 0
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#endif /* _SYSTEM_MANAGER_GEN5_H_ */
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