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d072065690
Adjust the DRAM timing settings for this board per ones provided by hardware department. The change is applied to the LPDDR4 MR11 register CA ODT configuration, from RZQ/6 to RZQ/3, which fixes stability issues on subset of boards. The DDR PHY PIE block has been updated accordingly. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <festevam@denx.de>