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1a4596601f
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
62 lines
1.6 KiB
C
62 lines
1.6 KiB
C
/*
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* Copyright (C) 2011 Matrix Vision GmbH
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* Andre Schwarz <andre.schwarz@matrix-vision.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __MERGERBOX_H__
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#define __MERGERBOX_H__
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#define MV_GPIO
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/*
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* GPIO Bank 1
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*/
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#define TFT_SPI_EN (0x80000000>>0)
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#define FPGA_CONFIG (0x80000000>>1)
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#define FPGA_STATUS (0x80000000>>2)
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#define FPGA_CONF_DONE (0x80000000>>3)
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#define FPGA_DIN (0x80000000>>4)
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#define FPGA_CCLK (0x80000000>>5)
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#define MAN_RST (0x80000000>>6)
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#define FPGA_SYS_RST (0x80000000>>7)
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#define WD_WDI (0x80000000>>8)
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#define TFT_RST (0x80000000>>9)
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#define HISCON_GPIO1 (0x80000000>>10)
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#define HISCON_GPIO2 (0x80000000>>11)
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#define B2B_GPIO2 (0x80000000>>12)
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#define CCU_GPIN (0x80000000>>13)
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#define CCU_GPOUT (0x80000000>>14)
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#define TFT_GPIO0 (0x80000000>>15)
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#define TFT_GPIO1 (0x80000000>>16)
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#define TFT_GPIO2 (0x80000000>>17)
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#define TFT_GPIO3 (0x80000000>>18)
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#define B2B_GPIO0 (0x80000000>>19)
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#define B2B_GPIO1 (0x80000000>>20)
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#define TFT_SPI_CPLD_CS (0x80000000>>21)
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#define TFT_SPI_CS (0x80000000>>22)
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#define CCU_PWR_EN (0x80000000>>23)
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#define B2B_GPIO3 (0x80000000>>24)
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#define CCU_PWR_STAT (0x80000000>>25)
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#define MV_GPIO1_DAT (FPGA_CONFIG|CCU_PWR_EN|TFT_SPI_CPLD_CS)
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#define MV_GPIO1_OUT (TFT_SPI_EN|FPGA_CONFIG|FPGA_DIN|FPGA_CCLK|CCU_PWR_EN| \
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TFT_SPI_CPLD_CS)
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#define MV_GPIO1_ODE (FPGA_CONFIG|MAN_RST)
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/*
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* GPIO Bank 2
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*/
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#define SPI_FLASH_WP (0x80000000>>10)
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#define SYS_EEPROM_WP (0x80000000>>11)
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#define SPI_FLASH_CS (0x80000000>>22)
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#define MV_GPIO2_DAT (SYS_EEPROM_WP|SPI_FLASH_CS)
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#define MV_GPIO2_OUT (SPI_FLASH_WP|SYS_EEPROM_WP|SPI_FLASH_CS)
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#define MV_GPIO2_ODE 0
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void mergerbox_tft_dim(u16 value);
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#endif
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