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https://github.com/smaeul/u-boot.git
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147 lines
4.4 KiB
C
147 lines
4.4 KiB
C
/*
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* Copyright (C) Freescale Semiconductor,Inc.
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* 2005, 2006. All rights reserved.
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*
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* Ed Swarthout (ed.swarthout@freescale.com)
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* Jason Jin (Jason.jin@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* PCIE Configuration space access support for PCIE Bridge
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*/
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#include <common.h>
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#include <pci.h>
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#if defined(CONFIG_PCI)
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void
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pci_mpc86xx_init(struct pci_controller *hose)
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{
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volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
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volatile ccsr_pex_t *pcie1 = &immap->im_pex1;
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u16 temp16;
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u32 temp32;
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volatile ccsr_gur_t *gur = &immap->im_gur;
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uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17;
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uint pcie1_host = (host1_agent == 2) || (host1_agent == 3);
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uint pcie1_agent = (host1_agent == 0) || (host1_agent == 1);
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uint devdisr = gur->devdisr;
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uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16;
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if ((io_sel == 2 || io_sel == 3 || io_sel == 5 || io_sel == 6 ||
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io_sel == 7 || io_sel == 0xf)
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&& !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
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printf("PCI-EXPRESS 1: Configured as %s \n",
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pcie1_agent ? "Agent" : "Host");
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if (pcie1_agent)
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return; /*Don't scan bus when configured as agent */
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printf(" Scanning PCIE bus");
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debug("0x%08x=0x%08x ",
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&pcie1->pme_msg_det,
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pcie1->pme_msg_det);
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if (pcie1->pme_msg_det) {
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pcie1->pme_msg_det = 0xffffffff;
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debug(" with errors. Clearing. Now 0x%08x",
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pcie1->pme_msg_det);
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}
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debug("\n");
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} else {
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printf("PCI-EXPRESS 1 disabled!\n");
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return;
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}
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/*
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* Set first_bus=0 only skipped B0:D0:F0 which is
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* a reserved device in M1575, but make it easy for
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* most of the scan process.
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*/
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hose->first_busno = 0x00;
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hose->last_busno = 0xfe;
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pcie_setup_indirect(hose, (CFG_IMMR + 0x8000), (CFG_IMMR + 0x8004));
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pci_hose_read_config_word(hose,
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PCI_BDF(0, 0, 0), PCI_COMMAND, &temp16);
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temp16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER |
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PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
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pci_hose_write_config_word(hose,
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PCI_BDF(0, 0, 0), PCI_COMMAND, temp16);
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pci_hose_write_config_word(hose, PCI_BDF(0, 0, 0), PCI_STATUS, 0xffff);
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pci_hose_write_config_byte(hose,
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PCI_BDF(0, 0, 0), PCI_LATENCY_TIMER, 0x80);
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pci_hose_read_config_dword(hose, PCI_BDF(0, 0, 0), PCI_PRIMARY_BUS,
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&temp32);
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temp32 = (temp32 & 0xff000000) | (0xff) | (0x0 << 8) | (0xfe << 16);
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pci_hose_write_config_dword(hose, PCI_BDF(0, 0, 0), PCI_PRIMARY_BUS,
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temp32);
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pcie1->powar1 = 0;
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pcie1->powar2 = 0;
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pcie1->piwar1 = 0;
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pcie1->piwar1 = 0;
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pcie1->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
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pcie1->powar1 = 0x8004401c; /* 512M MEM space */
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pcie1->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
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pcie1->potear1 = 0x00000000;
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pcie1->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
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pcie1->powar2 = 0x80088017; /* 16M IO space */
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pcie1->potar2 = 0x00000000;
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pcie1->potear2 = 0x00000000;
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pcie1->pitar1 = 0x00000000;
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pcie1->piwbar1 = 0x00000000;
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/* Enable, Prefetch, Local Mem, * Snoop R/W, 2G */
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pcie1->piwar1 = 0xa0f5501e;
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pci_set_region(hose->regions + 0,
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CFG_PCI_MEMORY_BUS,
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CFG_PCI_MEMORY_PHYS,
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CFG_PCI_MEMORY_SIZE,
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PCI_REGION_MEM | PCI_REGION_MEMORY);
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pci_set_region(hose->regions + 1,
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CFG_PCI1_MEM_BASE,
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CFG_PCI1_MEM_PHYS,
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CFG_PCI1_MEM_SIZE,
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PCI_REGION_MEM);
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pci_set_region(hose->regions + 2,
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CFG_PCI1_IO_BASE,
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CFG_PCI1_IO_PHYS,
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CFG_PCI1_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = 3;
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pci_register_hose(hose);
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hose->last_busno = pci_hose_scan(hose);
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debug("pcie_mpc86xx_init: last_busno %x\n", hose->last_busno);
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debug("pcie_mpc86xx init: current_busno %x\n ", hose->current_busno);
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printf("....PCIE1 scan & enumeration done\n");
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}
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#endif /* CONFIG_PCI */
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