mirror of
https://github.com/smaeul/u-boot.git
synced 2025-10-31 03:58:17 +00:00
174d728471
Update my and DPs email address to match current setup. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/aba5b19b9c5a95608829e86ad5cc4671c940f1bb.1688992543.git.michal.simek@amd.com
37 lines
943 B
C
37 lines
943 B
C
/* SPDX-License-Identifier: GPL-2.0 */
|
|
/*
|
|
* (C) Copyright 2015 Xilinx, Inc,
|
|
* Michal Simek <michal.simek@amd.com>
|
|
*/
|
|
|
|
#ifndef _ZYNQMPPL_H_
|
|
#define _ZYNQMPPL_H_
|
|
|
|
#include <xilinx.h>
|
|
#include <linux/bitops.h>
|
|
|
|
#define ZYNQMP_FPGA_OP_INIT (1 << 0)
|
|
#define ZYNQMP_FPGA_OP_LOAD (1 << 1)
|
|
#define ZYNQMP_FPGA_OP_DONE (1 << 2)
|
|
|
|
#define ZYNQMP_FPGA_FLAG_AUTHENTICATED BIT(2)
|
|
#define ZYNQMP_FPGA_FLAG_ENCRYPTED BIT(3)
|
|
|
|
#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT 15
|
|
#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK (0xf << \
|
|
ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT)
|
|
#define ZYNQMP_CSU_IDCODE_SVD_SHIFT 12
|
|
#define ZYNQMP_CSU_IDCODE_SVD_MASK (0x7 << ZYNQMP_CSU_IDCODE_SVD_SHIFT)
|
|
|
|
extern struct xilinx_fpga_op zynqmp_op;
|
|
|
|
#if CONFIG_IS_ENABLED(FPGA_LOAD_SECURE)
|
|
#define ZYNQMP_FPGA_FLAGS (FPGA_LEGACY | \
|
|
FPGA_XILINX_ZYNQMP_DDRAUTH | \
|
|
FPGA_XILINX_ZYNQMP_ENC)
|
|
#else
|
|
#define ZYNQMP_FPGA_FLAGS (FPGA_LEGACY)
|
|
#endif
|
|
|
|
#endif /* _ZYNQMPPL_H_ */
|