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	This follows the linux header rules to avoid conflict bitfields. Tested-by: Frank Wunderlich <frank-w@public-files.de> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
		
			
				
	
	
		
			37 lines
		
	
	
		
			860 B
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			37 lines
		
	
	
		
			860 B
		
	
	
	
		
			C
		
	
	
	
	
	
| /* SPDX-License-Identifier: GPL-2.0 */
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| /*
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|  * Copyright (C) 2019 MediaTek Inc.
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|  */
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| 
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| #ifndef _DT_BINDINGS_MTK_RESET_H_
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| #define _DT_BINDINGS_MTK_RESET_H_
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| 
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| /* PCIe Subsystem resets */
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| #define PCIE1_CORE_RST			19
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| #define PCIE1_MMIO_RST			20
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| #define PCIE1_HRST			21
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| #define PCIE1_USER_RST			22
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| #define PCIE1_PIPE_RST			23
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| #define PCIE0_CORE_RST			27
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| #define PCIE0_MMIO_RST			28
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| #define PCIE0_HRST			29
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| #define PCIE0_USER_RST			30
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| #define PCIE0_PIPE_RST			31
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| 
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| /* SSUSB Subsystem resets */
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| #define SSUSB_PHY_PWR_RST		3
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| #define SSUSB_MAC_PWR_RST		4
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| 
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| /* ETH Subsystem resets */
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| #define ETHSYS_SYS_RST			0
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| #define ETHSYS_MCM_RST			2
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| #define ETHSYS_HSDMA_RST		5
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| #define ETHSYS_FE_RST			6
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| #define ETHSYS_ESW_RST			16
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| #define ETHSYS_GMAC_RST			23
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| #define ETHSYS_EPHY_RST			24
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| #define ETHSYS_CRYPTO_RST		29
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| #define ETHSYS_PPE_RST			31
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| 
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| #endif /* _DT_BINDINGS_MTK_RESET_H_ */
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