mirror of
https://github.com/smaeul/u-boot.git
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310 lines
11 KiB
C
310 lines
11 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
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* Copyright (c) 2021, Linaro Ltd.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SC8180X_H
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#define _DT_BINDINGS_CLK_QCOM_GCC_SC8180X_H
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#define GCC_AGGRE_NOC_PCIE_TBU_CLK 0
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#define GCC_AGGRE_UFS_CARD_AXI_CLK 1
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#define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK 2
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#define GCC_AGGRE_UFS_PHY_AXI_CLK 3
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#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 4
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#define GCC_AGGRE_USB3_MP_AXI_CLK 5
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#define GCC_AGGRE_USB3_PRIM_AXI_CLK 6
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#define GCC_AGGRE_USB3_SEC_AXI_CLK 7
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#define GCC_BOOT_ROM_AHB_CLK 8
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#define GCC_CAMERA_HF_AXI_CLK 9
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#define GCC_CAMERA_SF_AXI_CLK 10
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#define GCC_CFG_NOC_USB3_MP_AXI_CLK 11
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#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 12
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#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 13
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#define GCC_CPUSS_AHB_CLK 14
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#define GCC_CPUSS_AHB_CLK_SRC 15
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#define GCC_CPUSS_RBCPR_CLK 16
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#define GCC_DDRSS_GPU_AXI_CLK 17
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#define GCC_DISP_HF_AXI_CLK 18
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#define GCC_DISP_SF_AXI_CLK 19
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#define GCC_EMAC_AXI_CLK 20
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#define GCC_EMAC_PTP_CLK 21
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#define GCC_EMAC_PTP_CLK_SRC 22
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#define GCC_EMAC_RGMII_CLK 23
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#define GCC_EMAC_RGMII_CLK_SRC 24
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#define GCC_EMAC_SLV_AHB_CLK 25
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#define GCC_GP1_CLK 26
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#define GCC_GP1_CLK_SRC 27
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#define GCC_GP2_CLK 28
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#define GCC_GP2_CLK_SRC 29
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#define GCC_GP3_CLK 30
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#define GCC_GP3_CLK_SRC 31
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#define GCC_GP4_CLK 32
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#define GCC_GP4_CLK_SRC 33
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#define GCC_GP5_CLK 34
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#define GCC_GP5_CLK_SRC 35
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#define GCC_GPU_GPLL0_CLK_SRC 36
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#define GCC_GPU_GPLL0_DIV_CLK_SRC 37
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#define GCC_GPU_MEMNOC_GFX_CLK 38
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#define GCC_GPU_SNOC_DVM_GFX_CLK 39
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#define GCC_NPU_AT_CLK 40
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#define GCC_NPU_AXI_CLK 41
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#define GCC_NPU_AXI_CLK_SRC 42
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#define GCC_NPU_GPLL0_CLK_SRC 43
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#define GCC_NPU_GPLL0_DIV_CLK_SRC 44
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#define GCC_NPU_TRIG_CLK 45
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#define GCC_PCIE0_PHY_REFGEN_CLK 46
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#define GCC_PCIE1_PHY_REFGEN_CLK 47
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#define GCC_PCIE2_PHY_REFGEN_CLK 48
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#define GCC_PCIE3_PHY_REFGEN_CLK 49
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#define GCC_PCIE_0_AUX_CLK 50
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#define GCC_PCIE_0_AUX_CLK_SRC 51
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#define GCC_PCIE_0_CFG_AHB_CLK 52
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#define GCC_PCIE_0_MSTR_AXI_CLK 53
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#define GCC_PCIE_0_PIPE_CLK 54
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#define GCC_PCIE_0_SLV_AXI_CLK 55
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#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 56
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#define GCC_PCIE_1_AUX_CLK 57
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#define GCC_PCIE_1_AUX_CLK_SRC 58
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#define GCC_PCIE_1_CFG_AHB_CLK 59
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#define GCC_PCIE_1_MSTR_AXI_CLK 60
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#define GCC_PCIE_1_PIPE_CLK 61
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#define GCC_PCIE_1_SLV_AXI_CLK 62
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#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 63
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#define GCC_PCIE_2_AUX_CLK 64
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#define GCC_PCIE_2_AUX_CLK_SRC 65
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#define GCC_PCIE_2_CFG_AHB_CLK 66
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#define GCC_PCIE_2_MSTR_AXI_CLK 67
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#define GCC_PCIE_2_PIPE_CLK 68
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#define GCC_PCIE_2_SLV_AXI_CLK 69
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#define GCC_PCIE_2_SLV_Q2A_AXI_CLK 70
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#define GCC_PCIE_3_AUX_CLK 71
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#define GCC_PCIE_3_AUX_CLK_SRC 72
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#define GCC_PCIE_3_CFG_AHB_CLK 73
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#define GCC_PCIE_3_MSTR_AXI_CLK 74
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#define GCC_PCIE_3_PIPE_CLK 75
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#define GCC_PCIE_3_SLV_AXI_CLK 76
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#define GCC_PCIE_3_SLV_Q2A_AXI_CLK 77
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#define GCC_PCIE_PHY_AUX_CLK 78
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#define GCC_PCIE_PHY_REFGEN_CLK_SRC 79
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#define GCC_PDM2_CLK 80
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#define GCC_PDM2_CLK_SRC 81
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#define GCC_PDM_AHB_CLK 82
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#define GCC_PDM_XO4_CLK 83
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#define GCC_PRNG_AHB_CLK 84
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#define GCC_QMIP_CAMERA_NRT_AHB_CLK 85
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#define GCC_QMIP_CAMERA_RT_AHB_CLK 86
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#define GCC_QMIP_DISP_AHB_CLK 87
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#define GCC_QMIP_VIDEO_CVP_AHB_CLK 88
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#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 89
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#define GCC_QSPI_1_CNOC_PERIPH_AHB_CLK 90
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#define GCC_QSPI_1_CORE_CLK 91
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#define GCC_QSPI_1_CORE_CLK_SRC 92
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#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 93
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#define GCC_QSPI_CORE_CLK 94
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#define GCC_QSPI_CORE_CLK_SRC 95
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#define GCC_QUPV3_WRAP0_S0_CLK 96
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#define GCC_QUPV3_WRAP0_S0_CLK_SRC 97
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#define GCC_QUPV3_WRAP0_S1_CLK 98
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#define GCC_QUPV3_WRAP0_S1_CLK_SRC 99
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#define GCC_QUPV3_WRAP0_S2_CLK 100
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#define GCC_QUPV3_WRAP0_S2_CLK_SRC 101
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#define GCC_QUPV3_WRAP0_S3_CLK 102
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#define GCC_QUPV3_WRAP0_S3_CLK_SRC 103
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#define GCC_QUPV3_WRAP0_S4_CLK 104
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#define GCC_QUPV3_WRAP0_S4_CLK_SRC 105
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#define GCC_QUPV3_WRAP0_S5_CLK 106
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#define GCC_QUPV3_WRAP0_S5_CLK_SRC 107
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#define GCC_QUPV3_WRAP0_S6_CLK 108
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#define GCC_QUPV3_WRAP0_S6_CLK_SRC 109
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#define GCC_QUPV3_WRAP0_S7_CLK 110
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#define GCC_QUPV3_WRAP0_S7_CLK_SRC 111
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#define GCC_QUPV3_WRAP1_S0_CLK 112
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#define GCC_QUPV3_WRAP1_S0_CLK_SRC 113
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#define GCC_QUPV3_WRAP1_S1_CLK 114
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#define GCC_QUPV3_WRAP1_S1_CLK_SRC 115
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#define GCC_QUPV3_WRAP1_S2_CLK 116
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#define GCC_QUPV3_WRAP1_S2_CLK_SRC 117
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#define GCC_QUPV3_WRAP1_S3_CLK 118
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#define GCC_QUPV3_WRAP1_S3_CLK_SRC 119
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#define GCC_QUPV3_WRAP1_S4_CLK 120
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#define GCC_QUPV3_WRAP1_S4_CLK_SRC 121
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#define GCC_QUPV3_WRAP1_S5_CLK 122
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#define GCC_QUPV3_WRAP1_S5_CLK_SRC 123
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#define GCC_QUPV3_WRAP2_S0_CLK 124
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#define GCC_QUPV3_WRAP2_S0_CLK_SRC 125
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#define GCC_QUPV3_WRAP2_S1_CLK 126
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#define GCC_QUPV3_WRAP2_S1_CLK_SRC 127
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#define GCC_QUPV3_WRAP2_S2_CLK 128
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#define GCC_QUPV3_WRAP2_S2_CLK_SRC 129
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#define GCC_QUPV3_WRAP2_S3_CLK 130
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#define GCC_QUPV3_WRAP2_S3_CLK_SRC 131
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#define GCC_QUPV3_WRAP2_S4_CLK 132
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#define GCC_QUPV3_WRAP2_S4_CLK_SRC 133
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#define GCC_QUPV3_WRAP2_S5_CLK 134
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#define GCC_QUPV3_WRAP2_S5_CLK_SRC 135
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#define GCC_QUPV3_WRAP_0_M_AHB_CLK 136
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#define GCC_QUPV3_WRAP_0_S_AHB_CLK 137
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#define GCC_QUPV3_WRAP_1_M_AHB_CLK 138
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#define GCC_QUPV3_WRAP_1_S_AHB_CLK 139
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#define GCC_QUPV3_WRAP_2_M_AHB_CLK 140
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#define GCC_QUPV3_WRAP_2_S_AHB_CLK 141
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#define GCC_SDCC2_AHB_CLK 142
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#define GCC_SDCC2_APPS_CLK 143
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#define GCC_SDCC2_APPS_CLK_SRC 144
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#define GCC_SDCC4_AHB_CLK 145
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#define GCC_SDCC4_APPS_CLK 146
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#define GCC_SDCC4_APPS_CLK_SRC 147
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#define GCC_SYS_NOC_CPUSS_AHB_CLK 148
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#define GCC_TSIF_AHB_CLK 149
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#define GCC_TSIF_INACTIVITY_TIMERS_CLK 150
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#define GCC_TSIF_REF_CLK 151
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#define GCC_TSIF_REF_CLK_SRC 152
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#define GCC_UFS_CARD_2_AHB_CLK 153
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#define GCC_UFS_CARD_2_AXI_CLK 154
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#define GCC_UFS_CARD_2_AXI_CLK_SRC 155
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#define GCC_UFS_CARD_2_ICE_CORE_CLK 156
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#define GCC_UFS_CARD_2_ICE_CORE_CLK_SRC 157
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#define GCC_UFS_CARD_2_PHY_AUX_CLK 158
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#define GCC_UFS_CARD_2_PHY_AUX_CLK_SRC 159
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#define GCC_UFS_CARD_2_RX_SYMBOL_0_CLK 160
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#define GCC_UFS_CARD_2_RX_SYMBOL_1_CLK 161
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#define GCC_UFS_CARD_2_TX_SYMBOL_0_CLK 162
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#define GCC_UFS_CARD_2_UNIPRO_CORE_CLK 163
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#define GCC_UFS_CARD_2_UNIPRO_CORE_CLK_SRC 164
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#define GCC_UFS_CARD_AHB_CLK 165
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#define GCC_UFS_CARD_AXI_CLK 166
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#define GCC_UFS_CARD_AXI_CLK_SRC 167
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#define GCC_UFS_CARD_AXI_HW_CTL_CLK 168
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#define GCC_UFS_CARD_ICE_CORE_CLK 169
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#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 170
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#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK 171
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#define GCC_UFS_CARD_PHY_AUX_CLK 172
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#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 173
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#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK 174
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#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 175
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#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 176
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#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 177
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#define GCC_UFS_CARD_UNIPRO_CORE_CLK 178
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#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 179
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#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK 180
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#define GCC_UFS_PHY_AHB_CLK 181
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#define GCC_UFS_PHY_AXI_CLK 182
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#define GCC_UFS_PHY_AXI_CLK_SRC 183
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#define GCC_UFS_PHY_AXI_HW_CTL_CLK 184
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#define GCC_UFS_PHY_ICE_CORE_CLK 185
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#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 186
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#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 187
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#define GCC_UFS_PHY_PHY_AUX_CLK 188
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#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 189
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#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 190
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#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 191
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#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 192
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#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 193
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#define GCC_UFS_PHY_UNIPRO_CORE_CLK 194
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#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 195
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#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 196
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#define GCC_USB30_MP_MASTER_CLK 197
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#define GCC_USB30_MP_MASTER_CLK_SRC 198
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#define GCC_USB30_MP_MOCK_UTMI_CLK 199
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#define GCC_USB30_MP_MOCK_UTMI_CLK_SRC 200
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#define GCC_USB30_MP_SLEEP_CLK 201
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#define GCC_USB30_PRIM_MASTER_CLK 202
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#define GCC_USB30_PRIM_MASTER_CLK_SRC 203
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK 204
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 205
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#define GCC_USB30_PRIM_SLEEP_CLK 206
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#define GCC_USB30_SEC_MASTER_CLK 207
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#define GCC_USB30_SEC_MASTER_CLK_SRC 208
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#define GCC_USB30_SEC_MOCK_UTMI_CLK 209
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#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 210
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#define GCC_USB30_SEC_SLEEP_CLK 211
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#define GCC_USB3_MP_PHY_AUX_CLK 212
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#define GCC_USB3_MP_PHY_AUX_CLK_SRC 213
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#define GCC_USB3_MP_PHY_COM_AUX_CLK 214
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#define GCC_USB3_MP_PHY_PIPE_0_CLK 215
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#define GCC_USB3_MP_PHY_PIPE_1_CLK 216
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#define GCC_USB3_PRIM_PHY_AUX_CLK 217
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#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 218
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#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 219
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#define GCC_USB3_PRIM_PHY_PIPE_CLK 220
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#define GCC_USB3_SEC_PHY_AUX_CLK 221
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#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 222
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#define GCC_USB3_SEC_PHY_COM_AUX_CLK 223
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#define GCC_USB3_SEC_PHY_PIPE_CLK 224
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#define GCC_VIDEO_AXI0_CLK 225
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#define GCC_VIDEO_AXI1_CLK 226
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#define GCC_VIDEO_AXIC_CLK 227
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#define GPLL0 228
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#define GPLL0_OUT_EVEN 229
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#define GPLL1 230
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#define GPLL4 231
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#define GPLL7 232
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#define GCC_PCIE_0_CLKREF_CLK 233
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#define GCC_PCIE_1_CLKREF_CLK 234
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#define GCC_PCIE_2_CLKREF_CLK 235
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#define GCC_PCIE_3_CLKREF_CLK 236
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#define GCC_USB3_PRIM_CLKREF_CLK 237
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#define GCC_USB3_SEC_CLKREF_CLK 238
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#define GCC_EMAC_BCR 0
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#define GCC_GPU_BCR 1
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#define GCC_MMSS_BCR 2
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#define GCC_NPU_BCR 3
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#define GCC_PCIE_0_BCR 4
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#define GCC_PCIE_0_PHY_BCR 5
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#define GCC_PCIE_1_BCR 6
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#define GCC_PCIE_1_PHY_BCR 7
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#define GCC_PCIE_2_BCR 8
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#define GCC_PCIE_2_PHY_BCR 9
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#define GCC_PCIE_3_BCR 10
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#define GCC_PCIE_3_PHY_BCR 11
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#define GCC_PCIE_PHY_BCR 12
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#define GCC_PDM_BCR 13
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#define GCC_PRNG_BCR 14
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#define GCC_QSPI_1_BCR 15
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#define GCC_QSPI_BCR 16
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#define GCC_QUPV3_WRAPPER_0_BCR 17
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#define GCC_QUPV3_WRAPPER_1_BCR 18
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#define GCC_QUPV3_WRAPPER_2_BCR 19
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#define GCC_QUSB2PHY_5_BCR 20
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#define GCC_QUSB2PHY_MP0_BCR 21
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#define GCC_QUSB2PHY_MP1_BCR 22
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#define GCC_QUSB2PHY_PRIM_BCR 23
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#define GCC_QUSB2PHY_SEC_BCR 24
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#define GCC_USB3_PHY_PRIM_SP0_BCR 25
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#define GCC_USB3_PHY_PRIM_SP1_BCR 26
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#define GCC_USB3_DP_PHY_PRIM_SP0_BCR 27
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#define GCC_USB3_DP_PHY_PRIM_SP1_BCR 28
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#define GCC_USB3_PHY_SEC_BCR 29
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#define GCC_USB3PHY_PHY_SEC_BCR 30
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#define GCC_SDCC2_BCR 31
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#define GCC_SDCC4_BCR 32
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#define GCC_TSIF_BCR 33
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#define GCC_UFS_CARD_2_BCR 34
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#define GCC_UFS_CARD_BCR 35
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#define GCC_UFS_PHY_BCR 36
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#define GCC_USB30_MP_BCR 37
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#define GCC_USB30_PRIM_BCR 38
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#define GCC_USB30_SEC_BCR 39
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#define GCC_USB_PHY_CFG_AHB2PHY_BCR 40
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#define GCC_VIDEO_AXIC_CLK_BCR 41
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#define GCC_VIDEO_AXI0_CLK_BCR 42
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#define GCC_VIDEO_AXI1_CLK_BCR 43
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#define GCC_USB3_DP_PHY_SEC_BCR 44
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/* GCC GDSCRs */
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#define EMAC_GDSC 0
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#define PCIE_0_GDSC 1
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#define PCIE_1_GDSC 2
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#define PCIE_2_GDSC 3
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#define PCIE_3_GDSC 4
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#define UFS_CARD_2_GDSC 5
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#define UFS_CARD_GDSC 6
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#define UFS_PHY_GDSC 7
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#define USB30_MP_GDSC 8
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#define USB30_PRIM_GDSC 9
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#define USB30_SEC_GDSC 10
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#endif
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