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b0866db2dc
Pull common board initialization code from V3M Eagle board into rcar-common/v3-common.c so it can be re-used by other V3M/V3H boards. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
47 lines
949 B
C
47 lines
949 B
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017-2023 Marek Vasut <marek.vasut+renesas@mailbox.org>
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*/
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#include <common.h>
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#include <clock_legacy.h>
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#include <asm/io.h>
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#define CPGWPR 0xE6150900
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#define CPGWPCR 0xE6150904
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/* PLL */
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#define PLL0CR 0xE61500D8
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#define PLL0_STC_MASK 0x7F000000
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#define PLL0_STC_OFFSET 24
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#define CLK2MHZ(clk) (clk / 1000 / 1000)
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void s_init(void)
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{
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struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
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struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
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u32 stc;
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/* Watchdog init */
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writel(0xA5A5A500, &rwdt->rwtcsra);
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writel(0xA5A5A500, &swdt->swtcsra);
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/* CPU frequency setting. Set to 0.8GHz */
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stc = ((800 / CLK2MHZ(get_board_sys_clk())) - 1) << PLL0_STC_OFFSET;
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clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
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}
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int board_early_init_f(void)
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{
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/* Unlock CPG access */
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writel(0xA5A5FFFF, CPGWPR);
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writel(0x5A5A0000, CPGWPCR);
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return 0;
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}
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int board_init(void)
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{
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return 0;
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}
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