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	The SR1500 board is a CycloneV based board, similar to the EBV SoCrates, equipped with the following devices: - SPI NOR - eMMC - Ethernet Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Pavel Machek <pavel@denx.de>
		
			
				
	
	
		
			102 lines
		
	
	
		
			1.5 KiB
		
	
	
	
		
			Plaintext
		
	
	
	
	
	
			
		
		
	
	
			102 lines
		
	
	
		
			1.5 KiB
		
	
	
	
		
			Plaintext
		
	
	
	
	
	
| /*
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|  * Copyright (C) 2015 Stefan Roese <sr@denx.de>
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|  *
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|  * SPDX-License-Identifier:	GPL-2.0+
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|  */
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| 
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| #include "socfpga_cyclone5.dtsi"
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| 
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| / {
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| 	model = "SoCFPGA Cyclone V SR1500";
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| 	compatible = "anonymous,socfpga-sr1500", "altr,socfpga-cyclone5", "altr,socfpga";
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| 
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| 	chosen {
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| 		bootargs = "console=ttyS0,115200";
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| 	};
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| 
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| 	aliases {
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| 		/*
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| 		 * This allows the ethaddr uboot environmnet variable
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| 		 * contents to be added to the gmac1 device tree blob.
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| 		 */
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| 		ethernet0 = &gmac1;
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| 	};
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| 
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| 	memory@0 {
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| 		name = "memory";
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| 		device_type = "memory";
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| 		reg = <0x0 0x40000000>; /* 1GB */
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| 	};
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| 
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| 	soc {
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| 		u-boot,dm-pre-reloc;
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| 	};
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| };
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| 
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| &gmac1 {
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| 	status = "okay";
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| 	phy-mode = "rgmii";
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| };
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| 
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| &gpio0 {
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| 	status = "okay";
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| };
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| 
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| &gpio1 {
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| 	status = "okay";
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| };
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| 
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| &gpio2 {
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| 	status = "okay";
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| };
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| 
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| &i2c0 {
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| 	status = "okay";
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| 	speed-mode = <0>;
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| };
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| 
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| &i2c1 {
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| 	status = "okay";
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| 	speed-mode = <0>;
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| };
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| 
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| &mmc0 {
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| 	status = "okay";
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| 	bus-width = <8>;
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| 	u-boot,dm-pre-reloc;
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| };
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| 
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| &uart0 {
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| 	status = "okay";
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| };
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| 
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| &usb1 {
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| 	status = "okay";
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| };
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| 
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| &watchdog0 {
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| 	status = "okay";
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| };
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| 
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| &qspi {
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| 	status = "okay";
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| 	u-boot,dm-pre-reloc;
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| 
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| 	flash0: n25q00@0 {
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| 		u-boot,dm-pre-reloc;
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| 		#address-cells = <1>;
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| 		#size-cells = <1>;
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| 		compatible = "n25q00", "spi-flash";
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| 		reg = <0>;      /* chip select */
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| 		spi-max-frequency = <50000000>;
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| 		m25p,fast-read;
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| 		page-size = <256>;
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| 		block-size = <16>; /* 2^16, 64KB */
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| 		read-delay = <4>;  /* delay value in read data capture register */
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| 		tshsl-ns = <50>;
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| 		tsd2d-ns = <50>;
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| 		tchsh-ns = <4>;
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| 		tslch-ns = <4>;
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| 	};
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| };
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