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1a4596601f
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
83 lines
3.0 KiB
C
83 lines
3.0 KiB
C
/*
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* Copyright 2009-2010 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/fsl_serdes.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include "fsl_corenet_serdes.h"
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static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
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[0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1,
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AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
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XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
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[0x5] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
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AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
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XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
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[0x8] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
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AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
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XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
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[0xd] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SGMII_FM2_DTSEC3,
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SGMII_FM2_DTSEC4, AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2,
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XAUI_FM2, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
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[0xe] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, SGMII_FM2_DTSEC3,
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SGMII_FM2_DTSEC4, AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2,
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XAUI_FM2, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
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[0xf] = {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
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SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, AURORA, AURORA, XAUI_FM2,
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XAUI_FM2, XAUI_FM2, XAUI_FM2, NONE, NONE, NONE, NONE},
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[0x10] = {PCIE1, PCIE1, PCIE3, PCIE3, SGMII_FM2_DTSEC1,
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SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
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AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
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NONE, NONE, NONE, NONE},
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[0x13] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
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AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
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XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
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[0x16] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
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AURORA, AURORA, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
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SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC1,
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SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4},
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[0x19] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
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AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, SGMII_FM1_DTSEC1,
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SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4},
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[0x1d] = {PCIE1, PCIE1, PCIE3, PCIE3, NONE, SRIO2, NONE, SRIO1,
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AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
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XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
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[0x22] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
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AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
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XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
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[0x25] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1,
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AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
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XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
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};
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#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
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uint16_t srds_lpd_b[SRDS_MAX_BANK];
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#endif
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enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
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{
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if (!serdes_lane_enabled(lane))
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return NONE;
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return serdes_cfg_tbl[cfg][lane];
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}
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int is_serdes_prtcl_valid(u32 prtcl) {
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int i;
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if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
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return 0;
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for (i = 0; i < SRDS_MAX_LANES; i++) {
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if (serdes_cfg_tbl[prtcl][i] != NONE)
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return 1;
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}
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return 0;
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}
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