mirror of
https://github.com/smaeul/u-boot.git
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184 lines
6.0 KiB
C
184 lines
6.0 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2023, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_5018_H
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#define _DT_BINDINGS_CLOCK_IPQ_GCC_5018_H
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#define GPLL0_MAIN 0
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#define GPLL0 1
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#define GPLL2_MAIN 2
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#define GPLL2 3
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#define GPLL4_MAIN 4
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#define GPLL4 5
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#define UBI32_PLL_MAIN 6
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#define UBI32_PLL 7
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#define ADSS_PWM_CLK_SRC 8
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#define BLSP1_QUP1_I2C_APPS_CLK_SRC 9
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#define BLSP1_QUP1_SPI_APPS_CLK_SRC 10
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#define BLSP1_QUP2_I2C_APPS_CLK_SRC 11
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#define BLSP1_QUP2_SPI_APPS_CLK_SRC 12
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#define BLSP1_QUP3_I2C_APPS_CLK_SRC 13
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#define BLSP1_QUP3_SPI_APPS_CLK_SRC 14
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#define BLSP1_UART1_APPS_CLK_SRC 15
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#define BLSP1_UART2_APPS_CLK_SRC 16
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#define CRYPTO_CLK_SRC 17
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#define GCC_ADSS_PWM_CLK 18
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#define GCC_BLSP1_AHB_CLK 19
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#define GCC_BLSP1_QUP1_I2C_APPS_CLK 20
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#define GCC_BLSP1_QUP1_SPI_APPS_CLK 21
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#define GCC_BLSP1_QUP2_I2C_APPS_CLK 22
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#define GCC_BLSP1_QUP2_SPI_APPS_CLK 23
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#define GCC_BLSP1_QUP3_I2C_APPS_CLK 24
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#define GCC_BLSP1_QUP3_SPI_APPS_CLK 25
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#define GCC_BLSP1_UART1_APPS_CLK 26
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#define GCC_BLSP1_UART2_APPS_CLK 27
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#define GCC_BTSS_LPO_CLK 28
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#define GCC_CMN_BLK_AHB_CLK 29
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#define GCC_CMN_BLK_SYS_CLK 30
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#define GCC_CRYPTO_AHB_CLK 31
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#define GCC_CRYPTO_AXI_CLK 32
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#define GCC_CRYPTO_CLK 33
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#define GCC_CRYPTO_PPE_CLK 34
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#define GCC_DCC_CLK 35
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#define GCC_GEPHY_RX_CLK 36
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#define GCC_GEPHY_TX_CLK 37
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#define GCC_GMAC0_CFG_CLK 38
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#define GCC_GMAC0_PTP_CLK 39
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#define GCC_GMAC0_RX_CLK 40
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#define GCC_GMAC0_SYS_CLK 41
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#define GCC_GMAC0_TX_CLK 42
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#define GCC_GMAC1_CFG_CLK 43
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#define GCC_GMAC1_PTP_CLK 44
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#define GCC_GMAC1_RX_CLK 45
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#define GCC_GMAC1_SYS_CLK 46
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#define GCC_GMAC1_TX_CLK 47
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#define GCC_GP1_CLK 48
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#define GCC_GP2_CLK 49
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#define GCC_GP3_CLK 50
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#define GCC_LPASS_CORE_AXIM_CLK 51
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#define GCC_LPASS_SWAY_CLK 52
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#define GCC_MDIO0_AHB_CLK 53
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#define GCC_MDIO1_AHB_CLK 54
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#define GCC_PCIE0_AHB_CLK 55
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#define GCC_PCIE0_AUX_CLK 56
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#define GCC_PCIE0_AXI_M_CLK 57
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#define GCC_PCIE0_AXI_S_BRIDGE_CLK 58
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#define GCC_PCIE0_AXI_S_CLK 59
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#define GCC_PCIE0_PIPE_CLK 60
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#define GCC_PCIE1_AHB_CLK 61
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#define GCC_PCIE1_AUX_CLK 62
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#define GCC_PCIE1_AXI_M_CLK 63
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#define GCC_PCIE1_AXI_S_BRIDGE_CLK 64
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#define GCC_PCIE1_AXI_S_CLK 65
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#define GCC_PCIE1_PIPE_CLK 66
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#define GCC_PRNG_AHB_CLK 67
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#define GCC_Q6_AXIM_CLK 68
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#define GCC_Q6_AXIM2_CLK 69
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#define GCC_Q6_AXIS_CLK 70
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#define GCC_Q6_AHB_CLK 71
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#define GCC_Q6_AHB_S_CLK 72
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#define GCC_Q6_TSCTR_1TO2_CLK 73
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#define GCC_Q6SS_ATBM_CLK 74
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#define GCC_Q6SS_PCLKDBG_CLK 75
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#define GCC_Q6SS_TRIG_CLK 76
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#define GCC_QDSS_AT_CLK 77
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#define GCC_QDSS_CFG_AHB_CLK 78
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#define GCC_QDSS_DAP_AHB_CLK 79
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#define GCC_QDSS_DAP_CLK 80
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#define GCC_QDSS_ETR_USB_CLK 81
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#define GCC_QDSS_EUD_AT_CLK 82
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#define GCC_QDSS_STM_CLK 83
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#define GCC_QDSS_TRACECLKIN_CLK 84
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#define GCC_QDSS_TSCTR_DIV8_CLK 85
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#define GCC_QPIC_AHB_CLK 86
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#define GCC_QPIC_CLK 87
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#define GCC_QPIC_IO_MACRO_CLK 88
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#define GCC_SDCC1_AHB_CLK 89
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#define GCC_SDCC1_APPS_CLK 90
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#define GCC_SLEEP_CLK_SRC 91
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#define GCC_SNOC_GMAC0_AHB_CLK 92
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#define GCC_SNOC_GMAC0_AXI_CLK 93
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#define GCC_SNOC_GMAC1_AHB_CLK 94
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#define GCC_SNOC_GMAC1_AXI_CLK 95
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#define GCC_SNOC_LPASS_AXIM_CLK 96
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#define GCC_SNOC_LPASS_SWAY_CLK 97
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#define GCC_SNOC_UBI0_AXI_CLK 98
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#define GCC_SYS_NOC_PCIE0_AXI_CLK 99
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#define GCC_SYS_NOC_PCIE1_AXI_CLK 100
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#define GCC_SYS_NOC_QDSS_STM_AXI_CLK 101
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#define GCC_SYS_NOC_USB0_AXI_CLK 102
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#define GCC_SYS_NOC_WCSS_AHB_CLK 103
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#define GCC_UBI0_AXI_CLK 104
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#define GCC_UBI0_CFG_CLK 105
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#define GCC_UBI0_CORE_CLK 106
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#define GCC_UBI0_DBG_CLK 107
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#define GCC_UBI0_NC_AXI_CLK 108
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#define GCC_UBI0_UTCM_CLK 109
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#define GCC_UNIPHY_AHB_CLK 110
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#define GCC_UNIPHY_RX_CLK 111
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#define GCC_UNIPHY_SYS_CLK 112
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#define GCC_UNIPHY_TX_CLK 113
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#define GCC_USB0_AUX_CLK 114
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#define GCC_USB0_EUD_AT_CLK 115
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#define GCC_USB0_LFPS_CLK 116
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#define GCC_USB0_MASTER_CLK 117
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#define GCC_USB0_MOCK_UTMI_CLK 118
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#define GCC_USB0_PHY_CFG_AHB_CLK 119
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#define GCC_USB0_SLEEP_CLK 120
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#define GCC_WCSS_ACMT_CLK 121
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#define GCC_WCSS_AHB_S_CLK 122
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#define GCC_WCSS_AXI_M_CLK 123
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#define GCC_WCSS_AXI_S_CLK 124
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#define GCC_WCSS_DBG_IFC_APB_BDG_CLK 125
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#define GCC_WCSS_DBG_IFC_APB_CLK 126
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#define GCC_WCSS_DBG_IFC_ATB_BDG_CLK 127
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#define GCC_WCSS_DBG_IFC_ATB_CLK 128
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#define GCC_WCSS_DBG_IFC_DAPBUS_BDG_CLK 129
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#define GCC_WCSS_DBG_IFC_DAPBUS_CLK 130
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#define GCC_WCSS_DBG_IFC_NTS_BDG_CLK 131
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#define GCC_WCSS_DBG_IFC_NTS_CLK 132
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#define GCC_WCSS_ECAHB_CLK 133
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#define GCC_XO_CLK 134
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#define GCC_XO_CLK_SRC 135
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#define GMAC0_RX_CLK_SRC 136
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#define GMAC0_TX_CLK_SRC 137
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#define GMAC1_RX_CLK_SRC 138
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#define GMAC1_TX_CLK_SRC 139
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#define GMAC_CLK_SRC 140
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#define GP1_CLK_SRC 141
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#define GP2_CLK_SRC 142
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#define GP3_CLK_SRC 143
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#define LPASS_AXIM_CLK_SRC 144
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#define LPASS_SWAY_CLK_SRC 145
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#define PCIE0_AUX_CLK_SRC 146
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#define PCIE0_AXI_CLK_SRC 147
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#define PCIE1_AUX_CLK_SRC 148
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#define PCIE1_AXI_CLK_SRC 149
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#define PCNOC_BFDCD_CLK_SRC 150
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#define Q6_AXI_CLK_SRC 151
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#define QDSS_AT_CLK_SRC 152
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#define QDSS_STM_CLK_SRC 153
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#define QDSS_TSCTR_CLK_SRC 154
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#define QDSS_TRACECLKIN_CLK_SRC 155
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#define QPIC_IO_MACRO_CLK_SRC 156
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#define SDCC1_APPS_CLK_SRC 157
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#define SYSTEM_NOC_BFDCD_CLK_SRC 158
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#define UBI0_AXI_CLK_SRC 159
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#define UBI0_CORE_CLK_SRC 160
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#define USB0_AUX_CLK_SRC 161
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#define USB0_LFPS_CLK_SRC 162
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#define USB0_MASTER_CLK_SRC 163
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#define USB0_MOCK_UTMI_CLK_SRC 164
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#define WCSS_AHB_CLK_SRC 165
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#define PCIE0_PIPE_CLK_SRC 166
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#define PCIE1_PIPE_CLK_SRC 167
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#define USB0_PIPE_CLK_SRC 168
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#define GCC_USB0_PIPE_CLK 169
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#define GMAC0_RX_DIV_CLK_SRC 170
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#define GMAC0_TX_DIV_CLK_SRC 171
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#define GMAC1_RX_DIV_CLK_SRC 172
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#define GMAC1_TX_DIV_CLK_SRC 173
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#endif
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