mirror of
https://github.com/smaeul/u-boot.git
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194 lines
6.7 KiB
C
194 lines
6.7 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SDX75_H
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#define _DT_BINDINGS_CLK_QCOM_GCC_SDX75_H
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/* GCC clocks */
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#define GPLL0 0
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#define GPLL0_OUT_EVEN 1
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#define GPLL4 2
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#define GPLL5 3
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#define GPLL6 4
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#define GPLL8 5
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#define GCC_AHB_PCIE_LINK_CLK 6
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#define GCC_BOOT_ROM_AHB_CLK 7
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#define GCC_EEE_EMAC0_CLK 8
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#define GCC_EEE_EMAC0_CLK_SRC 9
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#define GCC_EEE_EMAC1_CLK 10
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#define GCC_EEE_EMAC1_CLK_SRC 11
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#define GCC_EMAC0_AXI_CLK 12
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#define GCC_EMAC0_CC_SGMIIPHY_RX_CLK 13
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#define GCC_EMAC0_CC_SGMIIPHY_RX_CLK_SRC 14
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#define GCC_EMAC0_CC_SGMIIPHY_TX_CLK 15
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#define GCC_EMAC0_CC_SGMIIPHY_TX_CLK_SRC 16
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#define GCC_EMAC0_PHY_AUX_CLK 17
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#define GCC_EMAC0_PHY_AUX_CLK_SRC 18
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#define GCC_EMAC0_PTP_CLK 19
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#define GCC_EMAC0_PTP_CLK_SRC 20
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#define GCC_EMAC0_RGMII_CLK 21
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#define GCC_EMAC0_RGMII_CLK_SRC 22
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#define GCC_EMAC0_RPCS_RX_CLK 23
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#define GCC_EMAC0_RPCS_TX_CLK 24
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#define GCC_EMAC0_SGMIIPHY_MAC_RCLK_SRC 25
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#define GCC_EMAC0_SGMIIPHY_MAC_TCLK_SRC 26
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#define GCC_EMAC0_SLV_AHB_CLK 27
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#define GCC_EMAC0_XGXS_RX_CLK 28
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#define GCC_EMAC0_XGXS_TX_CLK 29
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#define GCC_EMAC1_AXI_CLK 30
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#define GCC_EMAC1_CC_SGMIIPHY_RX_CLK 31
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#define GCC_EMAC1_CC_SGMIIPHY_RX_CLK_SRC 32
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#define GCC_EMAC1_CC_SGMIIPHY_TX_CLK 33
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#define GCC_EMAC1_CC_SGMIIPHY_TX_CLK_SRC 34
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#define GCC_EMAC1_PHY_AUX_CLK 35
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#define GCC_EMAC1_PHY_AUX_CLK_SRC 36
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#define GCC_EMAC1_PTP_CLK 37
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#define GCC_EMAC1_PTP_CLK_SRC 38
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#define GCC_EMAC1_RGMII_CLK 39
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#define GCC_EMAC1_RGMII_CLK_SRC 40
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#define GCC_EMAC1_RPCS_RX_CLK 41
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#define GCC_EMAC1_RPCS_TX_CLK 42
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#define GCC_EMAC1_SGMIIPHY_MAC_RCLK_SRC 43
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#define GCC_EMAC1_SGMIIPHY_MAC_TCLK_SRC 44
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#define GCC_EMAC1_SLV_AHB_CLK 45
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#define GCC_EMAC1_XGXS_RX_CLK 46
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#define GCC_EMAC1_XGXS_TX_CLK 47
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#define GCC_EMAC_0_CLKREF_EN 48
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#define GCC_EMAC_1_CLKREF_EN 49
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#define GCC_GP1_CLK 50
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#define GCC_GP1_CLK_SRC 51
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#define GCC_GP2_CLK 52
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#define GCC_GP2_CLK_SRC 53
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#define GCC_GP3_CLK 54
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#define GCC_GP3_CLK_SRC 55
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#define GCC_PCIE_0_CLKREF_EN 56
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#define GCC_PCIE_1_AUX_CLK 57
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#define GCC_PCIE_1_AUX_PHY_CLK_SRC 58
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#define GCC_PCIE_1_CFG_AHB_CLK 59
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#define GCC_PCIE_1_CLKREF_EN 60
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#define GCC_PCIE_1_MSTR_AXI_CLK 61
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#define GCC_PCIE_1_PHY_RCHNG_CLK 62
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#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 63
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#define GCC_PCIE_1_PIPE_CLK 64
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#define GCC_PCIE_1_PIPE_CLK_SRC 65
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#define GCC_PCIE_1_PIPE_DIV2_CLK 66
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#define GCC_PCIE_1_PIPE_DIV2_CLK_SRC 67
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#define GCC_PCIE_1_SLV_AXI_CLK 68
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#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 69
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#define GCC_PCIE_2_AUX_CLK 70
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#define GCC_PCIE_2_AUX_PHY_CLK_SRC 71
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#define GCC_PCIE_2_CFG_AHB_CLK 72
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#define GCC_PCIE_2_CLKREF_EN 73
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#define GCC_PCIE_2_MSTR_AXI_CLK 74
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#define GCC_PCIE_2_PHY_RCHNG_CLK 75
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#define GCC_PCIE_2_PHY_RCHNG_CLK_SRC 76
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#define GCC_PCIE_2_PIPE_CLK 77
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#define GCC_PCIE_2_PIPE_CLK_SRC 78
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#define GCC_PCIE_2_PIPE_DIV2_CLK 79
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#define GCC_PCIE_2_PIPE_DIV2_CLK_SRC 80
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#define GCC_PCIE_2_SLV_AXI_CLK 81
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#define GCC_PCIE_2_SLV_Q2A_AXI_CLK 82
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#define GCC_PCIE_AUX_CLK 83
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#define GCC_PCIE_AUX_CLK_SRC 84
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#define GCC_PCIE_AUX_PHY_CLK_SRC 85
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#define GCC_PCIE_CFG_AHB_CLK 86
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#define GCC_PCIE_MSTR_AXI_CLK 87
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#define GCC_PCIE_PIPE_CLK 88
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#define GCC_PCIE_PIPE_CLK_SRC 89
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#define GCC_PCIE_RCHNG_PHY_CLK 90
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#define GCC_PCIE_RCHNG_PHY_CLK_SRC 91
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#define GCC_PCIE_SLEEP_CLK 92
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#define GCC_PCIE_SLV_AXI_CLK 93
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#define GCC_PCIE_SLV_Q2A_AXI_CLK 94
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#define GCC_PDM2_CLK 95
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#define GCC_PDM2_CLK_SRC 96
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#define GCC_PDM_AHB_CLK 97
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#define GCC_PDM_XO4_CLK 98
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#define GCC_QUPV3_WRAP0_CORE_2X_CLK 99
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#define GCC_QUPV3_WRAP0_CORE_CLK 100
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#define GCC_QUPV3_WRAP0_S0_CLK 101
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#define GCC_QUPV3_WRAP0_S0_CLK_SRC 102
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#define GCC_QUPV3_WRAP0_S1_CLK 103
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#define GCC_QUPV3_WRAP0_S1_CLK_SRC 104
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#define GCC_QUPV3_WRAP0_S2_CLK 105
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#define GCC_QUPV3_WRAP0_S2_CLK_SRC 106
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#define GCC_QUPV3_WRAP0_S3_CLK 107
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#define GCC_QUPV3_WRAP0_S3_CLK_SRC 108
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#define GCC_QUPV3_WRAP0_S4_CLK 109
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#define GCC_QUPV3_WRAP0_S4_CLK_SRC 110
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#define GCC_QUPV3_WRAP0_S5_CLK 111
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#define GCC_QUPV3_WRAP0_S5_CLK_SRC 112
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#define GCC_QUPV3_WRAP0_S6_CLK 113
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#define GCC_QUPV3_WRAP0_S6_CLK_SRC 114
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#define GCC_QUPV3_WRAP0_S7_CLK 115
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#define GCC_QUPV3_WRAP0_S7_CLK_SRC 116
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#define GCC_QUPV3_WRAP0_S8_CLK 117
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#define GCC_QUPV3_WRAP0_S8_CLK_SRC 118
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#define GCC_QUPV3_WRAP_0_M_AHB_CLK 119
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#define GCC_QUPV3_WRAP_0_S_AHB_CLK 120
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#define GCC_SDCC1_AHB_CLK 121
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#define GCC_SDCC1_APPS_CLK 122
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#define GCC_SDCC1_APPS_CLK_SRC 123
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#define GCC_SDCC2_AHB_CLK 124
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#define GCC_SDCC2_APPS_CLK 125
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#define GCC_SDCC2_APPS_CLK_SRC 126
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#define GCC_USB2_CLKREF_EN 127
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#define GCC_USB30_MASTER_CLK 128
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#define GCC_USB30_MASTER_CLK_SRC 129
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#define GCC_USB30_MOCK_UTMI_CLK 130
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#define GCC_USB30_MOCK_UTMI_CLK_SRC 131
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#define GCC_USB30_MOCK_UTMI_POSTDIV_CLK_SRC 132
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#define GCC_USB30_MSTR_AXI_CLK 133
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#define GCC_USB30_SLEEP_CLK 134
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#define GCC_USB30_SLV_AHB_CLK 135
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#define GCC_USB3_PHY_AUX_CLK 136
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#define GCC_USB3_PHY_AUX_CLK_SRC 137
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#define GCC_USB3_PHY_PIPE_CLK 138
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#define GCC_USB3_PHY_PIPE_CLK_SRC 139
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#define GCC_USB3_PRIM_CLKREF_EN 140
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#define GCC_USB_PHY_CFG_AHB2PHY_CLK 141
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#define GCC_XO_PCIE_LINK_CLK 142
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/* GCC power domains */
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#define GCC_EMAC0_GDSC 0
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#define GCC_EMAC1_GDSC 1
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#define GCC_PCIE_1_GDSC 2
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#define GCC_PCIE_1_PHY_GDSC 3
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#define GCC_PCIE_2_GDSC 4
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#define GCC_PCIE_2_PHY_GDSC 5
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#define GCC_PCIE_GDSC 6
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#define GCC_PCIE_PHY_GDSC 7
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#define GCC_USB30_GDSC 8
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#define GCC_USB3_PHY_GDSC 9
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/* GCC resets */
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#define GCC_EMAC0_BCR 0
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#define GCC_EMAC1_BCR 1
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#define GCC_EMMC_BCR 2
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#define GCC_PCIE_1_BCR 3
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#define GCC_PCIE_1_LINK_DOWN_BCR 4
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#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 5
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#define GCC_PCIE_1_PHY_BCR 6
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#define GCC_PCIE_2_BCR 7
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#define GCC_PCIE_2_LINK_DOWN_BCR 8
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#define GCC_PCIE_2_NOCSR_COM_PHY_BCR 9
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#define GCC_PCIE_2_PHY_BCR 10
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#define GCC_PCIE_BCR 11
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#define GCC_PCIE_LINK_DOWN_BCR 12
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#define GCC_PCIE_NOCSR_COM_PHY_BCR 13
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#define GCC_PCIE_PHY_BCR 14
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#define GCC_PCIE_PHY_CFG_AHB_BCR 15
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#define GCC_PCIE_PHY_COM_BCR 16
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#define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR 17
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#define GCC_QUSB2PHY_BCR 18
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#define GCC_TCSR_PCIE_BCR 19
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#define GCC_USB30_BCR 20
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#define GCC_USB3_PHY_BCR 21
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#define GCC_USB3PHY_PHY_BCR 22
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#define GCC_USB_PHY_CFG_AHB2PHY_BCR 23
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#define GCC_EMAC0_RGMII_CLK_ARES 24
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#endif
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