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smaeul-u-boot/arch/arm/dts/imx8mp-rsb3720-a1.dts
Marcel Ziswiler 84c5cd9b84 imx8mp-rsb3720-a1: fix pwms property warnings 
Fix the following build-time pwms property warnings:

w+arch/arm/dts/imx8mp-rsb3720-a1.dtb: Warning (pwms_property):
 /lvds_backlight@0:pwms: property size (12) too small for cell size 3
w+arch/arm/dts/imx8mp-rsb3720-a1.dtb: Warning (pwms_property):
 /lvds_backlight@1:pwms: property size (12) too small for cell size 3

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-07-25 16:12:01 +02:00

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2019 NXP
* Copyright 2022 Linaro
*/
/dts-v1/;
#include <dt-bindings/usb/pd.h>
#include "imx8mp.dtsi"
/ {
model = "Advantech i.MX8MPlus RSB3720A1 board";
compatible = "fsl,imx8mp-evk", "fsl,imx8mp";
aliases {
rtc0 = &s35390a;
rtc1 = &snvs_rtc;
};
chosen {
stdout-path = &uart3;
};
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0xc0000000>,
<0x1 0x00000000 0 0xc0000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
rpmsg_reserved: rpmsg@0x55800000 {
no-map;
reg = <0 0x55800000 0 0x800000>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_led>;
user {
label = "user";
gpios = <&gpio4 27 GPIO_ACTIVE_LOW>;
default-state = "off"; /* LED BLUE */
};
};
reg_usb1_host_vbus: regulator-usb1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb1_host_vbus";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1_vbus>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
reg_usdhc1_vmmc: regulator-usdhc1 {
compatible = "regulator-fixed";
regulator-name = "WLAN_EN";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>;
enable-active-high;
startup-delay-us = <100>;
off-on-delay-us = <12000>;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
//gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
startup-delay-us = <100>;
off-on-delay-us = <12000>;
};
lvds_backlight0: lvds_backlight@0 {
compatible = "pwm-backlight";
pwms = <&pwm2 0 5000000>;
status = "disabled";
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47 48 49
50 51 52 53 54 55 56 57 58 59
60 61 62 63 64 65 66 67 68 69
70 71 72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87 88 89
90 91 92 93 94 95 96 97 98 99
100>;
default-brightness-level = <80>;
};
lvds_backlight1: lvds_backlight@1 {
compatible = "pwm-backlight";
pwms = <&pwm3 0 5000000>;
status = "disabled";
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47 48 49
50 51 52 53 54 55 56 57 58 59
60 61 62 63 64 65 66 67 68 69
70 71 72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87 88 89
90 91 92 93 94 95 96 97 98 99
100>;
default-brightness-level = <80>;
};
rtl8367 {
compatible = "realtek,rtl8367b";
pinctrl-names = "default";
gpio-sda = <&gpio5 10 GPIO_ACTIVE_HIGH>;
gpio-sck = <&gpio5 11 GPIO_ACTIVE_HIGH>;
realtek,extif0 = <1 0 1 1 1 1 1 1 2>;
};
};
&clk {
init-on-array = <IMX8MP_CLK_HSIO_ROOT>;
};
&A53_0 {
cpu-supply = <&buck2_reg>;
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
#pwm-cells = <2>;
status = "okay";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
#pwm-cells = <2>;
status = "okay";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy1>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <4>;
at803x,eee-disabled;
at803x,vddio-1p8v;
};
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
status = "okay";
pmic: pca9450@25 {
reg = <0x25>;
compatible = "nxp,pca9450c", "nxp,pca9450b", "nxp,pca9450";
/* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
pinctrl-0 = <&pinctrl_pmic>;
gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
regulators {
#address-cells = <1>;
#size-cells = <0>;
pca9450,pmic-buck2-uses-i2c-dvs;
/* Run/Standby voltage */
pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>;
buck1_reg: regulator@0 {
reg = <0>;
regulator-compatible = "buck1";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck2_reg: regulator@1 {
reg = <1>;
regulator-compatible = "buck2";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck4_reg: regulator@3 {
reg = <3>;
regulator-compatible = "buck4";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
buck5_reg: regulator@4 {
reg = <4>;
regulator-compatible = "buck5";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
buck6_reg: regulator@5 {
reg = <5>;
regulator-compatible = "buck6";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
ldo1_reg: regulator@6 {
reg = <6>;
regulator-compatible = "ldo1";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo2_reg: regulator@7 {
reg = <7>;
regulator-compatible = "ldo2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1150000>;
regulator-boot-on;
regulator-always-on;
};
ldo3_reg: regulator@8 {
reg = <8>;
regulator-compatible = "ldo3";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo4_reg: regulator@9 {
reg = <9>;
regulator-compatible = "ldo4";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo5_reg: regulator@10 {
reg = <10>;
regulator-compatible = "ldo5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
};
};
s35390a: s35390a@30 {
compatible = "sii,s35390a", "sii,s35392a";
reg = <0x30>;
status = "okay";
};
gpio_exp2: tca9538@71 {
compatible = "nxp,pca9538";
reg = <0x71>;
gpio-controller;
#gpio-cells = <2>;
};
gpio_exp1: tca9538@70 {
compatible = "nxp,pca9538";
reg = <0x70>;
gpio-controller;
#gpio-cells = <2>;
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
status = "okay";
pca6416: gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c4>;
pinctrl-1 = <&pinctrl_i2c4_gpio>;
scl-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
status = "okay";
24c02@50 {
compatible = "fsl,24c02";
reg = <0x50>;
};
};
&snvs_pwrkey {
status = "okay";
};
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
status = "okay";
};
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
status = "okay";
};
&uart1 { /* BT */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
assigned-clocks = <&clk IMX8MP_CLK_UART1>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
fsl,uart-has-rtscts;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
/* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
assigned-clocks = <&clk IMX8MP_CLK_UART3>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
fsl,uart-has-rtscts;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
&usb3_phy0 {
fsl,phy-tx-vref-tune = <6>;
fsl,phy-tx-rise-tune = <0>;
fsl,phy-tx-preemp-amp-tune = <3>;
fsl,phy-comp-dis-tune = <7>;
fsl,pcs-tx-deemph-3p5db = <0x21>;
fsl,phy-pcs-tx-swing-full = <0x7f>;
status = "okay";
};
&usb3_0 {
status = "okay";
};
&usb_dwc3_0 {
dr_mode = "host";
status = "okay";
};
&usb3_phy1 {
fsl,phy-tx-preemp-amp-tune = <2>;
status = "okay";
};
&usb3_1 {
status = "okay";
};
&usb_dwc3_1 {
dr_mode = "host";
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
bus-width = <4>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
cqe-disabled;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "disabled";
};
&iomuxc {
pinctrl-names = "default";
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x116
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT 0x116
>;
};
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x19
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x19
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
>;
};
pinctrl_flexspi0: flexspi0grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2
MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82
MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82
MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82
MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82
MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
>;
};
pinctrl_gpio_led: gpioledgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x19
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI2_MISO__I2C4_SCL 0x400001c3
MX8MP_IOMUXC_ECSPI2_SS0__I2C4_SDA 0x400001c3
>;
};
pinctrl_i2c1_gpio: i2c1grp-gpio {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1c3
MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1c3
>;
};
pinctrl_i2c2_gpio: i2c2grp-gpio {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1c3
MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1c3
>;
};
pinctrl_i2c3_gpio: i2c3grp-gpio {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x1c3
MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x1c3
>;
};
pinctrl_i2c4_gpio: i2c4_gpio_grp {
fsl,pins = <
MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x1c3
MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x1c3
>;
};
pinctrl_pmic: pmicirq {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
>;
};
pinctrl_sai2: sai2grp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6
MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6
MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0xd6
MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6
MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6
MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6
MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6
MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140
MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140
MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140
MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140
MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49
MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49
>;
};
pinctrl_usb1_vbus: usb1grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x19
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
>;
};
pinctrl_usdhc1_gpio: usdhc1gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x19
MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x19
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp-100mhz {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp-200mhz {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_gpio: usdhc2grp-gpio {
fsl,pins = <
MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
>;
};
};
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