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				https://github.com/smaeul/u-boot.git
				synced 2025-10-31 03:58:17 +00:00 
			
		
		
		
	Rename arch-rmobile to arch-renesas and mach-rmobile to mach-renesas
because all the chips are made by Renesas, while only a subset of
them is from the R-Mobile line.
Use the following command to perform the rename, with manual move of
the directories using git mv and manual fix up to arch/arm/Makefile:
"
$ git grep -l '\<\(arch\|mach\)-rmobile\>' | \
  xargs -I {} sed -i 's@\<\(arch\|mach\)-rmobile\>@\1-renesas@g' {}
$ sed -i 's@rmobile@renesas@' board/*/*/Kconfig
"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
		
	
			
		
			
				
	
	
		
			104 lines
		
	
	
		
			2.0 KiB
		
	
	
	
		
			ArmAsm
		
	
	
	
	
	
			
		
		
	
	
			104 lines
		
	
	
		
			2.0 KiB
		
	
	
	
		
			ArmAsm
		
	
	
	
	
	
| /* SPDX-License-Identifier: GPL-2.0+ */
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| /*
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|  * arch/arm/cpu/armv8/rcar_gen3/lowlevel_init.S
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|  *	This file is lowlevel initialize routine.
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|  *
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|  * (C) Copyright 2015 Renesas Electronics Corporation
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|  *
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|  * This file is based on the arch/arm/cpu/armv8/start.S
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|  *
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|  * (C) Copyright 2013
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|  * David Feng <fenghua@phytium.com.cn>
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|  */
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| 
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| #include <asm-offsets.h>
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| #include <config.h>
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| #include <linux/linkage.h>
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| #include <asm/macro.h>
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| 
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| .align 8
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| .globl	rcar_atf_boot_args
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| rcar_atf_boot_args:
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| 	.dword 0
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| 	.dword 0
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| 	.dword 0
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| 	.dword 0
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| 
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| ENTRY(save_boot_params)
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| 	adr	x8, rcar_atf_boot_args
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| 	stp	x0, x1, [x8], #16
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| 	stp	x2, x3, [x8], #16
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| 	b	save_boot_params_ret
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| ENDPROC(save_boot_params)
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| 
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| .pushsection .text.s_init, "ax"
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| WEAK(s_init)
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| 	ret
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| ENDPROC(s_init)
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| .popsection
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| 
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| ENTRY(lowlevel_init)
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| 	mov	x29, lr			/* Save LR */
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| 
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| #ifndef CONFIG_ARMV8_MULTIENTRY
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| 	/*
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| 	 * For single-entry systems the lowlevel init is very simple.
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| 	 */
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| 	ldr	x0, =GICD_BASE
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| 	bl	gic_init_secure
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| 
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| #else /* CONFIG_ARMV8_MULTIENTRY is set */
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| 
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| #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
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| 	branch_if_slave x0, 1f
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| 	ldr	x0, =GICD_BASE
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| 	bl	gic_init_secure
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| 1:
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| #if defined(CONFIG_GICV3)
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| 	ldr	x0, =GICR_BASE
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| 	bl	gic_init_secure_percpu
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| #elif defined(CONFIG_GICV2)
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| 	ldr	x0, =GICD_BASE
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| 	ldr	x1, =GICC_BASE
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| 	bl	gic_init_secure_percpu
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| #endif
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| #endif
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| 
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| 	branch_if_master x0, 2f
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| 
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| 	/*
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| 	 * Slave should wait for master clearing spin table.
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| 	 * This sync prevent salves observing incorrect
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| 	 * value of spin table and jumping to wrong place.
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| 	 */
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| #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
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| #ifdef CONFIG_GICV2
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| 	ldr	x0, =GICC_BASE
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| #endif
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| 	bl	gic_wait_for_interrupt
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| #endif
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| 
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| 	/*
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| 	 * All slaves will enter EL2 and optionally EL1.
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| 	 */
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| 	adr	x4, lowlevel_in_el2
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| 	ldr	x5, =ES_TO_AARCH64
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| 	bl	armv8_switch_to_el2
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| 
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| lowlevel_in_el2:
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| #ifdef CONFIG_ARMV8_SWITCH_TO_EL1
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| 	adr	x4, lowlevel_in_el1
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| 	ldr	x5, =ES_TO_AARCH64
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| 	bl	armv8_switch_to_el1
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| 
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| lowlevel_in_el1:
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| #endif
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| #endif /* CONFIG_ARMV8_MULTIENTRY */
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| 
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| 	bl      s_init
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| 
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| 2:
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| 	mov	lr, x29			/* Restore LR */
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| 	ret
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| ENDPROC(lowlevel_init)
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