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03de305ec4
As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
81 lines
1.7 KiB
C
81 lines
1.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2019 Rockchip Electronics Co., Ltd
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*/
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#include <adc.h>
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#include <asm/arch-rockchip/grf_rk3308.h>
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#include <asm/arch-rockchip/hardware.h>
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#include <linux/bitops.h>
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#if defined(CONFIG_DEBUG_UART)
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#define GRF_BASE 0xff000000
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enum {
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GPIO1C7_SHIFT = 8,
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GPIO1C7_MASK = GENMASK(11, 8),
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GPIO1C7_GPIO = 0,
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GPIO1C7_UART1_RTSN,
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GPIO1C7_UART2_TX_M0,
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GPIO1C7_SPI2_MOSI,
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GPIO1C7_JTAG_TMS,
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GPIO1C6_SHIFT = 4,
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GPIO1C6_MASK = GENMASK(7, 4),
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GPIO1C6_GPIO = 0,
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GPIO1C6_UART1_CTSN,
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GPIO1C6_UART2_RX_M0,
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GPIO1C6_SPI2_MISO,
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GPIO1C6_JTAG_TCLK,
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GPIO4D3_SHIFT = 6,
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GPIO4D3_MASK = GENMASK(7, 6),
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GPIO4D3_GPIO = 0,
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GPIO4D3_SDMMC_D3,
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GPIO4D3_UART2_TX_M1,
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GPIO4D2_SHIFT = 4,
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GPIO4D2_MASK = GENMASK(5, 4),
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GPIO4D2_GPIO = 0,
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GPIO4D2_SDMMC_D2,
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GPIO4D2_UART2_RX_M1,
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UART2_IO_SEL_SHIFT = 2,
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UART2_IO_SEL_MASK = GENMASK(3, 2),
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UART2_IO_SEL_M0 = 0,
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UART2_IO_SEL_M1,
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UART2_IO_SEL_USB,
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};
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void board_debug_uart_init(void)
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{
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static struct rk3308_grf * const grf = (void *)GRF_BASE;
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/* Enable early UART2 channel m0 on the rk3308 */
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rk_clrsetreg(&grf->soc_con5, UART2_IO_SEL_MASK,
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UART2_IO_SEL_M0 << UART2_IO_SEL_SHIFT);
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rk_clrsetreg(&grf->gpio1ch_iomux,
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GPIO1C6_MASK | GPIO1C7_MASK,
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GPIO1C6_UART2_RX_M0 << GPIO1C6_SHIFT |
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GPIO1C7_UART2_TX_M0 << GPIO1C7_SHIFT);
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}
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#endif
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#define KEY_DOWN_MIN_VAL 0
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#define KEY_DOWN_MAX_VAL 30
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int rockchip_dnl_key_pressed(void)
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{
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unsigned int val;
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if (adc_channel_single_shot("saradc@ff1e0000", 1, &val)) {
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printf("%s read adc key val failed\n", __func__);
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return false;
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}
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if (val >= KEY_DOWN_MIN_VAL && val <= KEY_DOWN_MAX_VAL)
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return true;
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else
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return false;
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}
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