mirror of
https://github.com/smaeul/u-boot.git
synced 2025-10-28 10:38:19 +00:00
b8db88ab58
Milk-V Mars vendor board support package has value 0xa (multiplier=150) for both rx and tx delay. Upstream Linux has this as 1500 for both rx and tx delay. There is no documentation for why this should remain 1900 so correct it now. Mars CM and Mars CM Lite follow the same network phy delay values as Mars in the vendor board support package. Fixes: 92db23f7660de5897c8e3b91489b5b5780ffcd16 Signed-off-by: E Shattow <e@freeshell.de> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
476 lines
14 KiB
C
476 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2022 StarFive Technology Co., Ltd.
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* Author: Yanhong Wang<yanhong.wang@starfivetech.com>
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*/
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#include <asm/arch/eeprom.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/regs.h>
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#include <asm/arch/spl.h>
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#include <asm/io.h>
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#include <dt-bindings/clock/starfive,jh7110-crg.h>
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#include <fdt_support.h>
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#include <linux/libfdt.h>
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#include <log.h>
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#include <spl.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define JH7110_CLK_CPU_ROOT_OFFSET 0x0U
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#define JH7110_CLK_CPU_ROOT_SHIFT 24
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#define JH7110_CLK_CPU_ROOT_MASK GENMASK(29, 24)
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struct starfive_vf2_pro {
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const char *path;
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const char *name;
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const char *value;
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};
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static const struct starfive_vf2_pro milk_v_mars[] = {
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{"/soc/ethernet@16030000", "starfive,tx-use-rgmii-clk", NULL},
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{"/soc/ethernet@16040000", "starfive,tx-use-rgmii-clk", NULL},
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{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
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"motorcomm,tx-clk-adj-enabled", NULL},
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{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
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"motorcomm,tx-clk-100-inverted", NULL},
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{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
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"motorcomm,tx-clk-1000-inverted", NULL},
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{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
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"motorcomm,rx-clk-drv-microamp", "3970"},
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{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
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"motorcomm,rx-data-drv-microamp", "2910"},
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{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
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"rx-internal-delay-ps", "1500"},
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{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
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"tx-internal-delay-ps", "1500"},
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};
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static const struct starfive_vf2_pro starfive_vera[] = {
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{"/soc/ethernet@16030000/mdio/ethernet-phy@0", "rx-internal-delay-ps",
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"1900"},
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{"/soc/ethernet@16030000/mdio/ethernet-phy@0", "tx-internal-delay-ps",
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"1350"}
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};
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static const struct starfive_vf2_pro starfive_verb[] = {
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{"/soc/ethernet@16030000", "starfive,tx-use-rgmii-clk", NULL},
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{"/soc/ethernet@16040000", "starfive,tx-use-rgmii-clk", NULL},
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{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
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"motorcomm,tx-clk-adj-enabled", NULL},
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{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
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"motorcomm,tx-clk-100-inverted", NULL},
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{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
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"motorcomm,tx-clk-1000-inverted", NULL},
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{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
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"motorcomm,rx-clk-drv-microamp", "3970"},
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{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
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"motorcomm,rx-data-drv-microamp", "2910"},
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{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
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"rx-internal-delay-ps", "1500"},
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{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
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"motorcomm,tx-clk-adj-enabled", NULL},
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{ "/soc/ethernet@16040000/mdio/ethernet-phy@1",
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"motorcomm,tx-clk-100-inverted", NULL},
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{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
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"motorcomm,rx-clk-drv-microamp", "3970"},
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{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
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"motorcomm,rx-data-drv-microamp", "2910"},
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{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
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"rx-internal-delay-ps", "0"},
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{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
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"tx-internal-delay-ps", "0"},
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};
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static const struct starfive_vf2_pro star64_pine64[] = {
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{"/soc/ethernet@16030000", "starfive,tx-use-rgmii-clk", NULL},
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{"/soc/ethernet@16040000", "starfive,tx-use-rgmii-clk", NULL},
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{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
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"motorcomm,tx-clk-adj-enabled", NULL},
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{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
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"motorcomm,tx-clk-10-inverted", NULL},
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{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
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"motorcomm,tx-clk-100-inverted", NULL},
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{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
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"motorcomm,tx-clk-1000-inverted", NULL},
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{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
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"motorcomm,rx-clk-drv-microamp", "2910"},
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{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
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"motorcomm,rx-data-drv-microamp", "2910"},
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{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
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"rx-internal-delay-ps", "1900"},
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{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
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"tx-internal-delay-ps", "1500"},
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{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
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"motorcomm,tx-clk-adj-enabled", NULL},
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{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
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"motorcomm,tx-clk-10-inverted", NULL},
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{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
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"motorcomm,tx-clk-100-inverted", NULL},
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{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
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"motorcomm,rx-clk-drv-microamp", "2910"},
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{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
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"motorcomm,rx-data-drv-microamp", "2910"},
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{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
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"rx-internal-delay-ps", "0"},
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{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
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"tx-internal-delay-ps", "300"},
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};
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void spl_fdt_fixup_mars(void *fdt)
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{
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static const char compat[] = "milkv,mars\0starfive,jh7110";
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u32 phandle;
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u8 i;
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int offset;
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int ret;
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fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat, sizeof(compat));
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fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model",
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"Milk-V Mars");
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/* gmac0 */
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offset = fdt_path_offset(fdt, "/soc/clock-controller@17000000");
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phandle = fdt_get_phandle(fdt, offset);
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offset = fdt_path_offset(fdt, "/soc/ethernet@16030000");
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fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle);
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fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_AONCLK_GMAC0_TX);
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fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle);
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fdt_appendprop_u32(fdt, offset, "assigned-clock-parents",
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JH7110_AONCLK_GMAC0_RMII_RTX);
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/* gmac1 */
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fdt_setprop_string(fdt, fdt_path_offset(fdt, "/soc/ethernet@16040000"),
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"status", "disabled");
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for (i = 0; i < ARRAY_SIZE(milk_v_mars); i++) {
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offset = fdt_path_offset(fdt, milk_v_mars[i].path);
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if (milk_v_mars[i].value)
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ret = fdt_setprop_u32(fdt, offset, milk_v_mars[i].name,
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dectoul(milk_v_mars[i].value, NULL));
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else
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ret = fdt_setprop_empty(fdt, offset, milk_v_mars[i].name);
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if (ret) {
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pr_err("%s set prop %s fail.\n", __func__, milk_v_mars[i].name);
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break;
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}
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}
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}
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void spl_fdt_fixup_mars_cm(void *fdt)
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{
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const char *compat;
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const char *model;
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int compat_size;
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spl_fdt_fixup_mars(fdt);
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if (!get_mmc_size_from_eeprom()) {
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int offset;
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static const char
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compat_cm_lite[] = "milkv,mars-cm-lite\0starfive,jh7110";
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model = "Milk-V Mars CM Lite";
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compat = compat_cm_lite;
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compat_size = sizeof(compat_cm_lite);
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offset = fdt_path_offset(fdt, "/soc/pinctrl/mmc0-pins/mmc0-pins-rest");
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/* GPIOMUX(22, GPOUT_SYS_SDIO0_RST, GPOEN_ENABLE, GPI_NONE) */
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fdt_setprop_u32(fdt, offset, "pinmux", 0xff130016);
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} else {
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static const char
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compat_cm[] = "milkv,mars-cm\0starfive,jh7110";
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model = "Milk-V Mars CM";
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compat = compat_cm;
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compat_size = sizeof(compat_cm);
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}
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fdt_setprop(fdt, fdt_path_offset(fdt, "/"),
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"compatible", compat, compat_size);
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fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model", model);
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}
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void spl_fdt_fixup_version_a(void *fdt)
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{
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static const char compat[] = "starfive,visionfive-2-v1.2a\0starfive,jh7110";
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u32 phandle;
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u8 i;
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int offset;
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int ret;
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fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat, sizeof(compat));
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fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model",
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"StarFive VisionFive 2 v1.2A");
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offset = fdt_path_offset(fdt, "/soc/clock-controller@13020000");
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phandle = fdt_get_phandle(fdt, offset);
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offset = fdt_path_offset(fdt, "/soc/ethernet@16040000");
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fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle);
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fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_SYSCLK_GMAC1_TX);
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fdt_appendprop_u32(fdt, offset, "assigned-clocks", phandle);
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fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_SYSCLK_GMAC1_RX);
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fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle);
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fdt_appendprop_u32(fdt, offset, "assigned-clock-parents",
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JH7110_SYSCLK_GMAC1_RMII_RTX);
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fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", phandle);
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fdt_appendprop_u32(fdt, offset, "assigned-clock-parents",
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JH7110_SYSCLK_GMAC1_RMII_RTX);
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fdt_setprop_string(fdt, fdt_path_offset(fdt, "/soc/ethernet@16040000"),
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"phy-mode", "rmii");
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for (i = 0; i < ARRAY_SIZE(starfive_vera); i++) {
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offset = fdt_path_offset(fdt, starfive_vera[i].path);
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if (starfive_vera[i].value)
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ret = fdt_setprop_u32(fdt, offset, starfive_vera[i].name,
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dectoul(starfive_vera[i].value, NULL));
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else
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ret = fdt_setprop_empty(fdt, offset, starfive_vera[i].name);
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if (ret) {
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pr_err("%s set prop %s fail.\n", __func__, starfive_vera[i].name);
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break;
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}
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}
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}
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void spl_fdt_fixup_version_b(void *fdt)
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{
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static const char compat[] = "starfive,visionfive-2-v1.3b\0starfive,jh7110";
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u32 phandle;
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u8 i;
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int offset;
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int ret;
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fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat, sizeof(compat));
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fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model",
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"StarFive VisionFive 2 v1.3B");
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/* gmac0 */
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offset = fdt_path_offset(fdt, "/soc/clock-controller@17000000");
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phandle = fdt_get_phandle(fdt, offset);
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offset = fdt_path_offset(fdt, "/soc/ethernet@16030000");
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fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle);
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fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_AONCLK_GMAC0_TX);
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fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle);
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fdt_appendprop_u32(fdt, offset, "assigned-clock-parents",
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JH7110_AONCLK_GMAC0_RMII_RTX);
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/* gmac1 */
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offset = fdt_path_offset(fdt, "/soc/clock-controller@13020000");
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phandle = fdt_get_phandle(fdt, offset);
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offset = fdt_path_offset(fdt, "/soc/ethernet@16040000");
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fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle);
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fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_SYSCLK_GMAC1_TX);
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fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle);
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fdt_appendprop_u32(fdt, offset, "assigned-clock-parents",
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JH7110_SYSCLK_GMAC1_RMII_RTX);
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for (i = 0; i < ARRAY_SIZE(starfive_verb); i++) {
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offset = fdt_path_offset(fdt, starfive_verb[i].path);
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if (starfive_verb[i].value)
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ret = fdt_setprop_u32(fdt, offset, starfive_verb[i].name,
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dectoul(starfive_verb[i].value, NULL));
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else
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ret = fdt_setprop_empty(fdt, offset, starfive_verb[i].name);
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if (ret) {
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pr_err("%s set prop %s fail.\n", __func__, starfive_verb[i].name);
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break;
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}
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}
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}
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void spl_fdt_fixup_star64(void *fdt)
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{
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static const char compat[] = "pine64,star64\0starfive,jh7110";
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u32 phandle;
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u8 i;
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int offset;
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int ret;
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fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat, sizeof(compat));
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fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model",
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"Pine64 Star64");
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/* gmac0 */
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offset = fdt_path_offset(fdt, "/soc/clock-controller@17000000");
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phandle = fdt_get_phandle(fdt, offset);
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offset = fdt_path_offset(fdt, "/soc/ethernet@16030000");
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fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle);
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fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_AONCLK_GMAC0_TX);
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fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle);
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fdt_appendprop_u32(fdt, offset, "assigned-clock-parents",
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JH7110_AONCLK_GMAC0_RMII_RTX);
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/* gmac1 */
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offset = fdt_path_offset(fdt, "/soc/clock-controller@13020000");
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phandle = fdt_get_phandle(fdt, offset);
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offset = fdt_path_offset(fdt, "/soc/ethernet@16040000");
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fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle);
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fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_SYSCLK_GMAC1_TX);
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fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle);
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fdt_appendprop_u32(fdt, offset, "assigned-clock-parents",
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JH7110_SYSCLK_GMAC1_RMII_RTX);
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for (i = 0; i < ARRAY_SIZE(star64_pine64); i++) {
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offset = fdt_path_offset(fdt, star64_pine64[i].path);
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if (star64_pine64[i].value)
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ret = fdt_setprop_u32(fdt, offset, star64_pine64[i].name,
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dectoul(star64_pine64[i].value, NULL));
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else
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ret = fdt_setprop_empty(fdt, offset, star64_pine64[i].name);
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if (ret) {
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pr_err("%s set prop %s fail.\n", __func__, star64_pine64[i].name);
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break;
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}
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}
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}
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void spl_perform_fixups(struct spl_image_info *spl_image)
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{
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u8 version;
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const char *product_id;
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product_id = get_product_id_from_eeprom();
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if (!product_id) {
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pr_err("Can't read EEPROM\n");
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return;
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}
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if (!strncmp(product_id, "MARC", 4)) {
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spl_fdt_fixup_mars_cm(spl_image->fdt_addr);
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} else if (!strncmp(product_id, "MARS", 4)) {
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spl_fdt_fixup_mars(spl_image->fdt_addr);
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} else if (!strncmp(product_id, "VF7110", 6)) {
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version = get_pcb_revision_from_eeprom();
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switch (version) {
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case 'a':
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case 'A':
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spl_fdt_fixup_version_a(spl_image->fdt_addr);
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break;
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case 'b':
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case 'B':
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default:
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spl_fdt_fixup_version_b(spl_image->fdt_addr);
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break;
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};
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} else if (!strncmp(product_id, "STAR64", 6)) {
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spl_fdt_fixup_star64(spl_image->fdt_addr);
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} else {
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pr_err("Unknown product %s\n", product_id);
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};
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/* Update the memory size which read from eeprom or DT */
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fdt_fixup_memory(spl_image->fdt_addr, 0x40000000, gd->ram_size);
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}
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static void jh7110_jtag_init(void)
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{
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/* nTRST: GPIO36 */
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|
SYS_IOMUX_DOEN(36, HIGH);
|
|
SYS_IOMUX_DIN(36, 4);
|
|
/* TDI: GPIO61 */
|
|
SYS_IOMUX_DOEN(61, HIGH);
|
|
SYS_IOMUX_DIN(61, 19);
|
|
/* TMS: GPIO63 */
|
|
SYS_IOMUX_DOEN(63, HIGH);
|
|
SYS_IOMUX_DIN(63, 20);
|
|
/* TCK: GPIO60 */
|
|
SYS_IOMUX_DOEN(60, HIGH);
|
|
SYS_IOMUX_DIN(60, 29);
|
|
/* TDO: GPIO44 */
|
|
SYS_IOMUX_DOEN(44, 8);
|
|
SYS_IOMUX_DOUT(44, 22);
|
|
}
|
|
|
|
int spl_board_init_f(void)
|
|
{
|
|
int ret;
|
|
|
|
jh7110_jtag_init();
|
|
|
|
ret = spl_dram_init();
|
|
if (ret) {
|
|
debug("JH7110 DRAM init failed: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
u32 spl_boot_device(void)
|
|
{
|
|
u32 mode;
|
|
|
|
mode = in_le32(JH7110_BOOT_MODE_SELECT_REG)
|
|
& JH7110_BOOT_MODE_SELECT_MASK;
|
|
switch (mode) {
|
|
case 0:
|
|
return BOOT_DEVICE_SPI;
|
|
|
|
case 1:
|
|
return BOOT_DEVICE_MMC2;
|
|
|
|
case 2:
|
|
return BOOT_DEVICE_MMC1;
|
|
|
|
case 3:
|
|
return BOOT_DEVICE_UART;
|
|
|
|
default:
|
|
debug("Unsupported boot device 0x%x.\n", mode);
|
|
return BOOT_DEVICE_NONE;
|
|
}
|
|
}
|
|
|
|
void board_init_f(ulong dummy)
|
|
{
|
|
int ret;
|
|
|
|
ret = spl_early_init();
|
|
if (ret)
|
|
panic("spl_early_init() failed: %d\n", ret);
|
|
|
|
riscv_cpu_setup();
|
|
preloader_console_init();
|
|
|
|
/* Set the parent clock of cpu_root clock to pll0,
|
|
* it must be initialized here
|
|
*/
|
|
clrsetbits_le32(JH7110_SYS_CRG + JH7110_CLK_CPU_ROOT_OFFSET,
|
|
JH7110_CLK_CPU_ROOT_MASK,
|
|
BIT(JH7110_CLK_CPU_ROOT_SHIFT));
|
|
|
|
ret = spl_board_init_f();
|
|
if (ret) {
|
|
debug("spl_board_init_f init failed: %d\n", ret);
|
|
return;
|
|
}
|
|
}
|
|
|
|
#if CONFIG_IS_ENABLED(SPL_LOAD_FIT)
|
|
int board_fit_config_name_match(const char *name)
|
|
{
|
|
/* boot using first FIT config */
|
|
return 0;
|
|
}
|
|
#endif
|