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321 lines
12 KiB
C
321 lines
12 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2023, Linaro Limited
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SA8775P_H
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#define _DT_BINDINGS_CLK_QCOM_GCC_SA8775P_H
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/* GCC clocks */
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#define GCC_GPLL0 0
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#define GCC_GPLL0_OUT_EVEN 1
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#define GCC_GPLL1 2
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#define GCC_GPLL4 3
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#define GCC_GPLL5 4
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#define GCC_GPLL7 5
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#define GCC_GPLL9 6
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#define GCC_AGGRE_NOC_QUPV3_AXI_CLK 7
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#define GCC_AGGRE_UFS_CARD_AXI_CLK 8
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#define GCC_AGGRE_UFS_PHY_AXI_CLK 9
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#define GCC_AGGRE_USB2_PRIM_AXI_CLK 10
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#define GCC_AGGRE_USB3_PRIM_AXI_CLK 11
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#define GCC_AGGRE_USB3_SEC_AXI_CLK 12
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#define GCC_AHB2PHY0_CLK 13
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#define GCC_AHB2PHY2_CLK 14
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#define GCC_AHB2PHY3_CLK 15
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#define GCC_BOOT_ROM_AHB_CLK 16
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#define GCC_CAMERA_AHB_CLK 17
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#define GCC_CAMERA_HF_AXI_CLK 18
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#define GCC_CAMERA_SF_AXI_CLK 19
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#define GCC_CAMERA_THROTTLE_XO_CLK 20
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#define GCC_CAMERA_XO_CLK 21
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#define GCC_CFG_NOC_USB2_PRIM_AXI_CLK 22
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#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 23
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#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 24
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#define GCC_DDRSS_GPU_AXI_CLK 25
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#define GCC_DISP1_AHB_CLK 26
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#define GCC_DISP1_HF_AXI_CLK 27
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#define GCC_DISP1_XO_CLK 28
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#define GCC_DISP_AHB_CLK 29
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#define GCC_DISP_HF_AXI_CLK 30
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#define GCC_DISP_XO_CLK 31
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#define GCC_EDP_REF_CLKREF_EN 32
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#define GCC_EMAC0_AXI_CLK 33
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#define GCC_EMAC0_PHY_AUX_CLK 34
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#define GCC_EMAC0_PHY_AUX_CLK_SRC 35
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#define GCC_EMAC0_PTP_CLK 36
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#define GCC_EMAC0_PTP_CLK_SRC 37
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#define GCC_EMAC0_RGMII_CLK 38
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#define GCC_EMAC0_RGMII_CLK_SRC 39
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#define GCC_EMAC0_SLV_AHB_CLK 40
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#define GCC_EMAC1_AXI_CLK 41
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#define GCC_EMAC1_PHY_AUX_CLK 42
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#define GCC_EMAC1_PHY_AUX_CLK_SRC 43
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#define GCC_EMAC1_PTP_CLK 44
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#define GCC_EMAC1_PTP_CLK_SRC 45
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#define GCC_EMAC1_RGMII_CLK 46
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#define GCC_EMAC1_RGMII_CLK_SRC 47
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#define GCC_EMAC1_SLV_AHB_CLK 48
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#define GCC_GP1_CLK 49
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#define GCC_GP1_CLK_SRC 50
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#define GCC_GP2_CLK 51
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#define GCC_GP2_CLK_SRC 52
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#define GCC_GP3_CLK 53
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#define GCC_GP3_CLK_SRC 54
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#define GCC_GP4_CLK 55
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#define GCC_GP4_CLK_SRC 56
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#define GCC_GP5_CLK 57
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#define GCC_GP5_CLK_SRC 58
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#define GCC_GPU_CFG_AHB_CLK 59
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#define GCC_GPU_GPLL0_CLK_SRC 60
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#define GCC_GPU_GPLL0_DIV_CLK_SRC 61
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#define GCC_GPU_MEMNOC_GFX_CLK 62
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#define GCC_GPU_SNOC_DVM_GFX_CLK 63
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#define GCC_GPU_TCU_THROTTLE_AHB_CLK 64
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#define GCC_GPU_TCU_THROTTLE_CLK 65
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#define GCC_PCIE_0_AUX_CLK 66
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#define GCC_PCIE_0_AUX_CLK_SRC 67
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#define GCC_PCIE_0_CFG_AHB_CLK 68
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#define GCC_PCIE_0_MSTR_AXI_CLK 69
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#define GCC_PCIE_0_PHY_AUX_CLK 70
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#define GCC_PCIE_0_PHY_AUX_CLK_SRC 71
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#define GCC_PCIE_0_PHY_RCHNG_CLK 72
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#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 73
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#define GCC_PCIE_0_PIPE_CLK 74
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#define GCC_PCIE_0_PIPE_CLK_SRC 75
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#define GCC_PCIE_0_PIPE_DIV_CLK_SRC 76
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#define GCC_PCIE_0_PIPEDIV2_CLK 77
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#define GCC_PCIE_0_SLV_AXI_CLK 78
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#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 79
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#define GCC_PCIE_1_AUX_CLK 80
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#define GCC_PCIE_1_AUX_CLK_SRC 81
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#define GCC_PCIE_1_CFG_AHB_CLK 82
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#define GCC_PCIE_1_MSTR_AXI_CLK 83
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#define GCC_PCIE_1_PHY_AUX_CLK 84
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#define GCC_PCIE_1_PHY_AUX_CLK_SRC 85
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#define GCC_PCIE_1_PHY_RCHNG_CLK 86
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#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 87
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#define GCC_PCIE_1_PIPE_CLK 88
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#define GCC_PCIE_1_PIPE_CLK_SRC 89
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#define GCC_PCIE_1_PIPE_DIV_CLK_SRC 90
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#define GCC_PCIE_1_PIPEDIV2_CLK 91
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#define GCC_PCIE_1_SLV_AXI_CLK 92
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#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 93
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#define GCC_PCIE_CLKREF_EN 94
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#define GCC_PCIE_THROTTLE_CFG_CLK 95
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#define GCC_PDM2_CLK 96
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#define GCC_PDM2_CLK_SRC 97
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#define GCC_PDM_AHB_CLK 98
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#define GCC_PDM_XO4_CLK 99
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#define GCC_QMIP_CAMERA_NRT_AHB_CLK 100
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#define GCC_QMIP_CAMERA_RT_AHB_CLK 101
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#define GCC_QMIP_DISP1_AHB_CLK 102
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#define GCC_QMIP_DISP1_ROT_AHB_CLK 103
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#define GCC_QMIP_DISP_AHB_CLK 104
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#define GCC_QMIP_DISP_ROT_AHB_CLK 105
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#define GCC_QMIP_VIDEO_CVP_AHB_CLK 106
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#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 107
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#define GCC_QMIP_VIDEO_VCPU_AHB_CLK 108
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#define GCC_QUPV3_WRAP0_CORE_2X_CLK 109
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#define GCC_QUPV3_WRAP0_CORE_CLK 110
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#define GCC_QUPV3_WRAP0_S0_CLK 111
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#define GCC_QUPV3_WRAP0_S0_CLK_SRC 112
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#define GCC_QUPV3_WRAP0_S1_CLK 113
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#define GCC_QUPV3_WRAP0_S1_CLK_SRC 114
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#define GCC_QUPV3_WRAP0_S2_CLK 115
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#define GCC_QUPV3_WRAP0_S2_CLK_SRC 116
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#define GCC_QUPV3_WRAP0_S3_CLK 117
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#define GCC_QUPV3_WRAP0_S3_CLK_SRC 118
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#define GCC_QUPV3_WRAP0_S4_CLK 119
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#define GCC_QUPV3_WRAP0_S4_CLK_SRC 120
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#define GCC_QUPV3_WRAP0_S5_CLK 121
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#define GCC_QUPV3_WRAP0_S5_CLK_SRC 122
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#define GCC_QUPV3_WRAP0_S6_CLK 123
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#define GCC_QUPV3_WRAP0_S6_CLK_SRC 124
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#define GCC_QUPV3_WRAP1_CORE_2X_CLK 125
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#define GCC_QUPV3_WRAP1_CORE_CLK 126
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#define GCC_QUPV3_WRAP1_S0_CLK 127
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#define GCC_QUPV3_WRAP1_S0_CLK_SRC 128
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#define GCC_QUPV3_WRAP1_S1_CLK 129
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#define GCC_QUPV3_WRAP1_S1_CLK_SRC 130
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#define GCC_QUPV3_WRAP1_S2_CLK 131
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#define GCC_QUPV3_WRAP1_S2_CLK_SRC 132
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#define GCC_QUPV3_WRAP1_S3_CLK 133
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#define GCC_QUPV3_WRAP1_S3_CLK_SRC 134
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#define GCC_QUPV3_WRAP1_S4_CLK 135
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#define GCC_QUPV3_WRAP1_S4_CLK_SRC 136
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#define GCC_QUPV3_WRAP1_S5_CLK 137
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#define GCC_QUPV3_WRAP1_S5_CLK_SRC 138
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#define GCC_QUPV3_WRAP1_S6_CLK 139
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#define GCC_QUPV3_WRAP1_S6_CLK_SRC 140
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#define GCC_QUPV3_WRAP2_CORE_2X_CLK 141
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#define GCC_QUPV3_WRAP2_CORE_CLK 142
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#define GCC_QUPV3_WRAP2_S0_CLK 143
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#define GCC_QUPV3_WRAP2_S0_CLK_SRC 144
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#define GCC_QUPV3_WRAP2_S1_CLK 145
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#define GCC_QUPV3_WRAP2_S1_CLK_SRC 146
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#define GCC_QUPV3_WRAP2_S2_CLK 147
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#define GCC_QUPV3_WRAP2_S2_CLK_SRC 148
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#define GCC_QUPV3_WRAP2_S3_CLK 149
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#define GCC_QUPV3_WRAP2_S3_CLK_SRC 150
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#define GCC_QUPV3_WRAP2_S4_CLK 151
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#define GCC_QUPV3_WRAP2_S4_CLK_SRC 152
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#define GCC_QUPV3_WRAP2_S5_CLK 153
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#define GCC_QUPV3_WRAP2_S5_CLK_SRC 154
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#define GCC_QUPV3_WRAP2_S6_CLK 155
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#define GCC_QUPV3_WRAP2_S6_CLK_SRC 156
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#define GCC_QUPV3_WRAP3_CORE_2X_CLK 157
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#define GCC_QUPV3_WRAP3_CORE_CLK 158
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#define GCC_QUPV3_WRAP3_QSPI_CLK 159
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#define GCC_QUPV3_WRAP3_S0_CLK 160
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#define GCC_QUPV3_WRAP3_S0_CLK_SRC 161
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#define GCC_QUPV3_WRAP3_S0_DIV_CLK_SRC 162
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#define GCC_QUPV3_WRAP_0_M_AHB_CLK 163
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#define GCC_QUPV3_WRAP_0_S_AHB_CLK 164
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#define GCC_QUPV3_WRAP_1_M_AHB_CLK 165
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#define GCC_QUPV3_WRAP_1_S_AHB_CLK 166
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#define GCC_QUPV3_WRAP_2_M_AHB_CLK 167
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#define GCC_QUPV3_WRAP_2_S_AHB_CLK 168
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#define GCC_QUPV3_WRAP_3_M_AHB_CLK 169
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#define GCC_QUPV3_WRAP_3_S_AHB_CLK 170
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#define GCC_SDCC1_AHB_CLK 171
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#define GCC_SDCC1_APPS_CLK 172
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#define GCC_SDCC1_APPS_CLK_SRC 173
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#define GCC_SDCC1_ICE_CORE_CLK 174
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#define GCC_SDCC1_ICE_CORE_CLK_SRC 175
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#define GCC_SGMI_CLKREF_EN 176
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#define GCC_TSCSS_AHB_CLK 177
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#define GCC_TSCSS_CNTR_CLK_SRC 178
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#define GCC_TSCSS_ETU_CLK 179
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#define GCC_TSCSS_GLOBAL_CNTR_CLK 180
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#define GCC_UFS_CARD_AHB_CLK 181
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#define GCC_UFS_CARD_AXI_CLK 182
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#define GCC_UFS_CARD_AXI_CLK_SRC 183
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#define GCC_UFS_CARD_ICE_CORE_CLK 184
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#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 185
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#define GCC_UFS_CARD_PHY_AUX_CLK 186
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#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 187
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#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 188
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#define GCC_UFS_CARD_RX_SYMBOL_0_CLK_SRC 189
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#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 190
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#define GCC_UFS_CARD_RX_SYMBOL_1_CLK_SRC 191
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#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 192
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#define GCC_UFS_CARD_TX_SYMBOL_0_CLK_SRC 193
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#define GCC_UFS_CARD_UNIPRO_CORE_CLK 194
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#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 195
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#define GCC_UFS_PHY_AHB_CLK 196
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#define GCC_UFS_PHY_AXI_CLK 197
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#define GCC_UFS_PHY_AXI_CLK_SRC 198
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#define GCC_UFS_PHY_ICE_CORE_CLK 199
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#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 200
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#define GCC_UFS_PHY_PHY_AUX_CLK 201
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#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 202
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#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 203
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#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 204
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#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 205
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#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 206
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#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 207
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#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 208
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#define GCC_UFS_PHY_UNIPRO_CORE_CLK 209
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#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 210
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#define GCC_USB20_MASTER_CLK 211
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#define GCC_USB20_MASTER_CLK_SRC 212
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#define GCC_USB20_MOCK_UTMI_CLK 213
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#define GCC_USB20_MOCK_UTMI_CLK_SRC 214
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#define GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC 215
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#define GCC_USB20_SLEEP_CLK 216
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#define GCC_USB30_PRIM_MASTER_CLK 217
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#define GCC_USB30_PRIM_MASTER_CLK_SRC 218
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK 219
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 220
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#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 221
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#define GCC_USB30_PRIM_SLEEP_CLK 222
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#define GCC_USB30_SEC_MASTER_CLK 223
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#define GCC_USB30_SEC_MASTER_CLK_SRC 224
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#define GCC_USB30_SEC_MOCK_UTMI_CLK 225
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#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 226
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#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 227
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#define GCC_USB30_SEC_SLEEP_CLK 228
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#define GCC_USB3_PRIM_PHY_AUX_CLK 229
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#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 230
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#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 231
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#define GCC_USB3_PRIM_PHY_PIPE_CLK 232
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#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 233
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#define GCC_USB3_SEC_PHY_AUX_CLK 234
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#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 235
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#define GCC_USB3_SEC_PHY_COM_AUX_CLK 236
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#define GCC_USB3_SEC_PHY_PIPE_CLK 237
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#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 238
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#define GCC_USB_CLKREF_EN 239
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#define GCC_VIDEO_AHB_CLK 240
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#define GCC_VIDEO_AXI0_CLK 241
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#define GCC_VIDEO_AXI1_CLK 242
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#define GCC_VIDEO_XO_CLK 243
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#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 244
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#define GCC_UFS_PHY_AXI_HW_CTL_CLK 245
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#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 246
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#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 247
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#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 248
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/* GCC resets */
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#define GCC_CAMERA_BCR 0
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#define GCC_DISPLAY1_BCR 1
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#define GCC_DISPLAY_BCR 2
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#define GCC_EMAC0_BCR 3
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#define GCC_EMAC1_BCR 4
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#define GCC_GPU_BCR 5
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#define GCC_MMSS_BCR 6
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#define GCC_PCIE_0_BCR 7
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#define GCC_PCIE_0_LINK_DOWN_BCR 8
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#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 9
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#define GCC_PCIE_0_PHY_BCR 10
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#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 11
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#define GCC_PCIE_1_BCR 12
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#define GCC_PCIE_1_LINK_DOWN_BCR 13
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#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 14
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#define GCC_PCIE_1_PHY_BCR 15
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#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 16
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#define GCC_PDM_BCR 17
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#define GCC_QUPV3_WRAPPER_0_BCR 18
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#define GCC_QUPV3_WRAPPER_1_BCR 19
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#define GCC_QUPV3_WRAPPER_2_BCR 20
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#define GCC_QUPV3_WRAPPER_3_BCR 21
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#define GCC_SDCC1_BCR 22
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#define GCC_TSCSS_BCR 23
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#define GCC_UFS_CARD_BCR 24
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#define GCC_UFS_PHY_BCR 25
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#define GCC_USB20_PRIM_BCR 26
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#define GCC_USB2_PHY_PRIM_BCR 27
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#define GCC_USB2_PHY_SEC_BCR 28
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#define GCC_USB30_PRIM_BCR 29
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#define GCC_USB30_SEC_BCR 30
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#define GCC_USB3_DP_PHY_PRIM_BCR 31
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#define GCC_USB3_DP_PHY_SEC_BCR 32
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#define GCC_USB3_PHY_PRIM_BCR 33
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#define GCC_USB3_PHY_SEC_BCR 34
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#define GCC_USB3_PHY_TERT_BCR 35
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#define GCC_USB3_UNIPHY_MP0_BCR 36
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#define GCC_USB3_UNIPHY_MP1_BCR 37
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#define GCC_USB3PHY_PHY_PRIM_BCR 38
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#define GCC_USB3PHY_PHY_SEC_BCR 39
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#define GCC_USB3UNIPHY_PHY_MP0_BCR 40
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#define GCC_USB3UNIPHY_PHY_MP1_BCR 41
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#define GCC_USB_PHY_CFG_AHB2PHY_BCR 42
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#define GCC_VIDEO_BCR 43
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#define GCC_VIDEO_AXI0_CLK_ARES 44
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#define GCC_VIDEO_AXI1_CLK_ARES 45
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/* GCC GDSCs */
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#define PCIE_0_GDSC 0
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#define PCIE_1_GDSC 1
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#define UFS_CARD_GDSC 2
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#define UFS_PHY_GDSC 3
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#define USB20_PRIM_GDSC 4
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#define USB30_PRIM_GDSC 5
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#define USB30_SEC_GDSC 6
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#define EMAC0_GDSC 7
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#define EMAC1_GDSC 8
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#endif /* _DT_BINDINGS_CLK_QCOM_GCC_SA8775P_H */
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