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df4c82f014
This patch adds reset bits for MediaTek MT7988 Signed-off-by: Sam Shih <sam.shih@mediatek.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
32 lines
786 B
C
32 lines
786 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2023 MediaTek Inc.
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*/
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#ifndef _DT_BINDINGS_MTK_RESET_H_
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#define _DT_BINDINGS_MTK_RESET_H_
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/* ETHDMA Subsystem resets */
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#define ETHDMA_FE_RST 6
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#define ETHDMA_PMTR_RST 8
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#define ETHDMA_GMAC_RST 23
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#define ETHDMA_WDMA0_RST 24
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#define ETHDMA_WDMA1_RST 25
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#define ETHDMA_WDMA2_RST 26
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#define ETHDMA_PPE0_RST 29
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#define ETHDMA_PPE1_RST 30
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#define ETHDMA_PPE2_RST 31
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/* ETHWARP Subsystem resets */
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#define ETHWARP_GSW_RST 9
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#define ETHWARP_EIP197_RST 10
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#define ETHWARP_WOCPU0_RST 32
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#define ETHWARP_WOCPU1_RST 33
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#define ETHWARP_WOCPU2_RST 34
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#define ETHWARP_WOX_NET_MUX_RST 35
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#define ETHWARP_WED0_RST 36
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#define ETHWARP_WED1_RST 37
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#define ETHWARP_WED2_RST 38
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#endif /* _DT_BINDINGS_MTK_RESET_H_ */
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