mirror of
https://github.com/smaeul/u-boot.git
synced 2025-11-03 21:48:15 +00:00
24ec3dea4b
- In a number of cases, use CONFIG_ARCH_EXYNOS[45] rather than CONFIG_EXYNOS[45] - In other cases, test for CONFIG_ARCH_EXYNOS or CONFIG_ARCH_S5PC1XX - Migrate specific SoC CONFIG values to Kconfig - Use CONFIG_TARGET_x rather than CONFIG_x - Migrate other CONFIG_EXYNOS_x symbols to Kconfig - Reference CONFIG_EXYNOS_RELOCATE_CODE_BASE directly as EXYNOS_RELOCATE_CODE_BASE - Rename CONFIG_S5P_PA_SYSRAM to CONFIG_SMP_PEN_ADDR to match the rest of U-Boot usage. Cc: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Tom Rini <trini@konsulko.com>
557 lines
15 KiB
C
557 lines
15 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Machine Specific Values for EXYNOS4012 based board
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*
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* Copyright (C) 2011 Samsung Electronics
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*/
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#ifndef _ORIGEN_SETUP_H
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#define _ORIGEN_SETUP_H
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#include <config.h>
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#include <asm/arch/cpu.h>
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/* Bus Configuration Register Address */
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#define ASYNC_CONFIG 0x10010350
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/* CLK_SRC_CPU */
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#define MUX_HPM_SEL_MOUTAPLL 0x0
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#define MUX_HPM_SEL_SCLKMPLL 0x1
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#define MUX_CORE_SEL_MOUTAPLL 0x0
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#define MUX_CORE_SEL_SCLKMPLL 0x1
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#define MUX_MPLL_SEL_FILPLL 0x0
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#define MUX_MPLL_SEL_MOUTMPLLFOUT 0x1
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#define MUX_APLL_SEL_FILPLL 0x0
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#define MUX_APLL_SEL_MOUTMPLLFOUT 0x1
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#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL_MOUTAPLL << 20) \
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| (MUX_CORE_SEL_MOUTAPLL << 16) \
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| (MUX_MPLL_SEL_MOUTMPLLFOUT << 8)\
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| (MUX_APLL_SEL_MOUTMPLLFOUT << 0))
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/* CLK_DIV_CPU0 */
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#define APLL_RATIO 0x0
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#define PCLK_DBG_RATIO 0x1
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#define ATB_RATIO 0x3
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#define PERIPH_RATIO 0x3
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#define COREM1_RATIO 0x7
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#define COREM0_RATIO 0x3
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#define CORE_RATIO 0x0
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#define CLK_DIV_CPU0_VAL ((APLL_RATIO << 24) \
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| (PCLK_DBG_RATIO << 20) \
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| (ATB_RATIO << 16) \
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| (PERIPH_RATIO << 12) \
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| (COREM1_RATIO << 8) \
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| (COREM0_RATIO << 4) \
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| (CORE_RATIO << 0))
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/* CLK_DIV_CPU1 */
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#define HPM_RATIO 0x0
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#define COPY_RATIO 0x3
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#define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) | (COPY_RATIO))
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/* CLK_SRC_DMC */
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#define MUX_PWI_SEL_XXTI 0x0
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#define MUX_PWI_SEL_XUSBXTI 0x1
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#define MUX_PWI_SEL_SCLK_HDMI24M 0x2
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#define MUX_PWI_SEL_SCLK_USBPHY0 0x3
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#define MUX_PWI_SEL_SCLK_USBPHY1 0x4
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#define MUX_PWI_SEL_SCLK_HDMIPHY 0x5
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#define MUX_PWI_SEL_SCLKMPLL 0x6
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#define MUX_PWI_SEL_SCLKEPLL 0x7
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#define MUX_PWI_SEL_SCLKVPLL 0x8
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#define MUX_DPHY_SEL_SCLKMPLL 0x0
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#define MUX_DPHY_SEL_SCLKAPLL 0x1
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#define MUX_DMC_BUS_SEL_SCLKMPLL 0x0
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#define MUX_DMC_BUS_SEL_SCLKAPLL 0x1
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#define CLK_SRC_DMC_VAL ((MUX_PWI_SEL_XUSBXTI << 16) \
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| (MUX_DPHY_SEL_SCLKMPLL << 8) \
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| (MUX_DMC_BUS_SEL_SCLKMPLL << 4))
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/* CLK_DIV_DMC0 */
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#define CORE_TIMERS_RATIO 0x1
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#define COPY2_RATIO 0x3
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#define DMCP_RATIO 0x1
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#define DMCD_RATIO 0x1
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#define DMC_RATIO 0x1
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#define DPHY_RATIO 0x1
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#define ACP_PCLK_RATIO 0x1
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#define ACP_RATIO 0x3
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#define CLK_DIV_DMC0_VAL ((CORE_TIMERS_RATIO << 28) \
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| (COPY2_RATIO << 24) \
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| (DMCP_RATIO << 20) \
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| (DMCD_RATIO << 16) \
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| (DMC_RATIO << 12) \
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| (DPHY_RATIO << 8) \
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| (ACP_PCLK_RATIO << 4) \
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| (ACP_RATIO << 0))
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/* CLK_DIV_DMC1 */
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#define DPM_RATIO 0x1
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#define DVSEM_RATIO 0x1
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#define PWI_RATIO 0x1
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#define CLK_DIV_DMC1_VAL ((DPM_RATIO << 24) \
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| (DVSEM_RATIO << 16) \
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| (PWI_RATIO << 8))
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/* CLK_SRC_TOP0 */
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#define MUX_ONENAND_SEL_ACLK_133 0x0
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#define MUX_ONENAND_SEL_ACLK_160 0x1
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#define MUX_ACLK_133_SEL_SCLKMPLL 0x0
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#define MUX_ACLK_133_SEL_SCLKAPLL 0x1
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#define MUX_ACLK_160_SEL_SCLKMPLL 0x0
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#define MUX_ACLK_160_SEL_SCLKAPLL 0x1
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#define MUX_ACLK_100_SEL_SCLKMPLL 0x0
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#define MUX_ACLK_100_SEL_SCLKAPLL 0x1
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#define MUX_ACLK_200_SEL_SCLKMPLL 0x0
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#define MUX_ACLK_200_SEL_SCLKAPLL 0x1
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#define MUX_VPLL_SEL_FINPLL 0x0
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#define MUX_VPLL_SEL_FOUTVPLL 0x1
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#define MUX_EPLL_SEL_FINPLL 0x0
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#define MUX_EPLL_SEL_FOUTEPLL 0x1
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#define MUX_ONENAND_1_SEL_MOUTONENAND 0x0
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#define MUX_ONENAND_1_SEL_SCLKVPLL 0x1
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#define CLK_SRC_TOP0_VAL ((MUX_ONENAND_SEL_ACLK_133 << 28) \
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| (MUX_ACLK_133_SEL_SCLKMPLL << 24) \
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| (MUX_ACLK_160_SEL_SCLKMPLL << 20) \
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| (MUX_ACLK_100_SEL_SCLKMPLL << 16) \
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| (MUX_ACLK_200_SEL_SCLKMPLL << 12) \
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| (MUX_VPLL_SEL_FINPLL << 8) \
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| (MUX_EPLL_SEL_FINPLL << 4)\
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| (MUX_ONENAND_1_SEL_MOUTONENAND << 0))
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/* CLK_SRC_TOP1 */
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#define VPLLSRC_SEL_FINPLL 0x0
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#define VPLLSRC_SEL_SCLKHDMI24M 0x1
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#define CLK_SRC_TOP1_VAL (VPLLSRC_SEL_FINPLL)
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/* CLK_DIV_TOP */
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#define ONENAND_RATIO 0x0
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#define ACLK_133_RATIO 0x5
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#define ACLK_160_RATIO 0x4
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#define ACLK_100_RATIO 0x7
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#define ACLK_200_RATIO 0x3
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#define CLK_DIV_TOP_VAL ((ONENAND_RATIO << 16) \
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| (ACLK_133_RATIO << 12)\
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| (ACLK_160_RATIO << 8) \
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| (ACLK_100_RATIO << 4) \
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| (ACLK_200_RATIO << 0))
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/* CLK_SRC_LEFTBUS */
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#define MUX_GDL_SEL_SCLKMPLL 0x0
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#define MUX_GDL_SEL_SCLKAPLL 0x1
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#define CLK_SRC_LEFTBUS_VAL (MUX_GDL_SEL_SCLKMPLL)
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/* CLK_DIV_LEFTBUS */
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#define GPL_RATIO 0x1
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#define GDL_RATIO 0x3
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#define CLK_DIV_LEFTBUS_VAL ((GPL_RATIO << 4) | (GDL_RATIO))
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/* CLK_SRC_RIGHTBUS */
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#define MUX_GDR_SEL_SCLKMPLL 0x0
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#define MUX_GDR_SEL_SCLKAPLL 0x1
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#define CLK_SRC_RIGHTBUS_VAL (MUX_GDR_SEL_SCLKMPLL)
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/* CLK_DIV_RIGHTBUS */
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#define GPR_RATIO 0x1
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#define GDR_RATIO 0x3
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#define CLK_DIV_RIGHTBUS_VAL ((GPR_RATIO << 4) | (GDR_RATIO))
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/* CLK_SRS_FSYS: 6 = SCLKMPLL */
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#define SATA_SEL_SCLKMPLL 0
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#define SATA_SEL_SCLKAPLL 1
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#define MMC_SEL_XXTI 0
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#define MMC_SEL_XUSBXTI 1
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#define MMC_SEL_SCLK_HDMI24M 2
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#define MMC_SEL_SCLK_USBPHY0 3
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#define MMC_SEL_SCLK_USBPHY1 4
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#define MMC_SEL_SCLK_HDMIPHY 5
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#define MMC_SEL_SCLKMPLL 6
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#define MMC_SEL_SCLKEPLL 7
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#define MMC_SEL_SCLKVPLL 8
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#define MMCC0_SEL MMC_SEL_SCLKMPLL
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#define MMCC1_SEL MMC_SEL_SCLKMPLL
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#define MMCC2_SEL MMC_SEL_SCLKMPLL
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#define MMCC3_SEL MMC_SEL_SCLKMPLL
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#define MMCC4_SEL MMC_SEL_SCLKMPLL
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#define CLK_SRC_FSYS_VAL ((SATA_SEL_SCLKMPLL << 24) \
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| (MMCC4_SEL << 16) \
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| (MMCC3_SEL << 12) \
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| (MMCC2_SEL << 8) \
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| (MMCC1_SEL << 4) \
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| (MMCC0_SEL << 0))
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/* SCLK_MMC[0-4] = MOUTMMC[0-4]/(MMC[0-4]_RATIO + 1)/(MMC[0-4]_PRE_RATIO +1) */
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/* CLK_DIV_FSYS1 */
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#define MMC0_RATIO 0xF
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#define MMC0_PRE_RATIO 0x0
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#define MMC1_RATIO 0xF
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#define MMC1_PRE_RATIO 0x0
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#define CLK_DIV_FSYS1_VAL ((MMC1_PRE_RATIO << 24) \
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| (MMC1_RATIO << 16) \
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| (MMC0_PRE_RATIO << 8) \
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| (MMC0_RATIO << 0))
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/* CLK_DIV_FSYS2 */
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#define MMC2_RATIO 0xF
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#define MMC2_PRE_RATIO 0x0
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#define MMC3_RATIO 0xF
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#define MMC3_PRE_RATIO 0x0
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#define CLK_DIV_FSYS2_VAL ((MMC3_PRE_RATIO << 24) \
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| (MMC3_RATIO << 16) \
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| (MMC2_PRE_RATIO << 8) \
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| (MMC2_RATIO << 0))
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/* CLK_DIV_FSYS3 */
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#define MMC4_RATIO 0xF
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#define MMC4_PRE_RATIO 0x0
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#define CLK_DIV_FSYS3_VAL ((MMC4_PRE_RATIO << 8) \
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| (MMC4_RATIO << 0))
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/* CLK_SRC_PERIL0 */
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#define UART_SEL_XXTI 0
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#define UART_SEL_XUSBXTI 1
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#define UART_SEL_SCLK_HDMI24M 2
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#define UART_SEL_SCLK_USBPHY0 3
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#define UART_SEL_SCLK_USBPHY1 4
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#define UART_SEL_SCLK_HDMIPHY 5
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#define UART_SEL_SCLKMPLL 6
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#define UART_SEL_SCLKEPLL 7
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#define UART_SEL_SCLKVPLL 8
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#define UART0_SEL UART_SEL_SCLKMPLL
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#define UART1_SEL UART_SEL_SCLKMPLL
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#define UART2_SEL UART_SEL_SCLKMPLL
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#define UART3_SEL UART_SEL_SCLKMPLL
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#define UART4_SEL UART_SEL_SCLKMPLL
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#define CLK_SRC_PERIL0_VAL ((UART4_SEL << 16) \
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| (UART3_SEL << 12) \
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| (UART2_SEL << 8) \
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| (UART1_SEL << 4) \
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| (UART0_SEL << 0))
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/* SCLK_UART[0-4] = MOUTUART[0-4]/(UART[0-4]_RATIO + 1) */
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/* CLK_DIV_PERIL0 */
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#define UART0_RATIO 7
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#define UART1_RATIO 7
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#define UART2_RATIO 7
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#define UART3_RATIO 7
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#define UART4_RATIO 7
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#define CLK_DIV_PERIL0_VAL ((UART4_RATIO << 16) \
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| (UART3_RATIO << 12) \
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| (UART2_RATIO << 8) \
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| (UART1_RATIO << 4) \
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| (UART0_RATIO << 0))
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/* Clock Source CAM/FIMC */
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/* CLK_SRC_CAM */
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#define CAM0_SEL_XUSBXTI 1
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#define CAM1_SEL_XUSBXTI 1
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#define CSIS0_SEL_XUSBXTI 1
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#define CSIS1_SEL_XUSBXTI 1
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#define FIMC_SEL_SCLKMPLL 6
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#define FIMC0_LCLK_SEL FIMC_SEL_SCLKMPLL
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#define FIMC1_LCLK_SEL FIMC_SEL_SCLKMPLL
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#define FIMC2_LCLK_SEL FIMC_SEL_SCLKMPLL
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#define FIMC3_LCLK_SEL FIMC_SEL_SCLKMPLL
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#define CLK_SRC_CAM_VAL ((CSIS1_SEL_XUSBXTI << 28) \
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| (CSIS0_SEL_XUSBXTI << 24) \
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| (CAM1_SEL_XUSBXTI << 20) \
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| (CAM0_SEL_XUSBXTI << 16) \
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| (FIMC3_LCLK_SEL << 12) \
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| (FIMC2_LCLK_SEL << 8) \
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| (FIMC1_LCLK_SEL << 4) \
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| (FIMC0_LCLK_SEL << 0))
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/* SCLK CAM */
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/* CLK_DIV_CAM */
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#define FIMC0_LCLK_RATIO 4
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#define FIMC1_LCLK_RATIO 4
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#define FIMC2_LCLK_RATIO 4
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#define FIMC3_LCLK_RATIO 4
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#define CLK_DIV_CAM_VAL ((FIMC3_LCLK_RATIO << 12) \
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| (FIMC2_LCLK_RATIO << 8) \
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| (FIMC1_LCLK_RATIO << 4) \
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| (FIMC0_LCLK_RATIO << 0))
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/* SCLK MFC */
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/* CLK_SRC_MFC */
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#define MFC_SEL_MPLL 0
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#define MOUTMFC_0 0
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#define MFC_SEL MOUTMFC_0
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#define MFC_0_SEL MFC_SEL_MPLL
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#define CLK_SRC_MFC_VAL ((MFC_SEL << 8) | (MFC_0_SEL))
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/* CLK_DIV_MFC */
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#define MFC_RATIO 3
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#define CLK_DIV_MFC_VAL (MFC_RATIO)
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/* SCLK G3D */
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/* CLK_SRC_G3D */
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#define G3D_SEL_MPLL 0
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#define MOUTG3D_0 0
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#define G3D_SEL MOUTG3D_0
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#define G3D_0_SEL G3D_SEL_MPLL
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#define CLK_SRC_G3D_VAL ((G3D_SEL << 8) | (G3D_0_SEL))
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/* CLK_DIV_G3D */
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#define G3D_RATIO 1
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#define CLK_DIV_G3D_VAL (G3D_RATIO)
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/* SCLK LCD0 */
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/* CLK_SRC_LCD0 */
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#define FIMD_SEL_SCLKMPLL 6
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#define MDNIE0_SEL_XUSBXTI 1
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#define MDNIE_PWM0_SEL_XUSBXTI 1
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#define MIPI0_SEL_XUSBXTI 1
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#define CLK_SRC_LCD0_VAL ((MIPI0_SEL_XUSBXTI << 12) \
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| (MDNIE_PWM0_SEL_XUSBXTI << 8) \
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| (MDNIE0_SEL_XUSBXTI << 4) \
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| (FIMD_SEL_SCLKMPLL << 0))
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/* CLK_DIV_LCD0 */
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#define FIMD0_RATIO 4
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#define CLK_DIV_LCD0_VAL (FIMD0_RATIO)
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/* Required period to generate a stable clock output */
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/* PLL_LOCK_TIME */
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#define PLL_LOCKTIME 0x1C20
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/* PLL Values */
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#define DISABLE 0
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#define ENABLE 1
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#define SET_PLL(mdiv, pdiv, sdiv) ((ENABLE << 31)\
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| (mdiv << 16) \
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| (pdiv << 8) \
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| (sdiv << 0))
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/* APLL_CON0 */
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#define APLL_MDIV 0xFA
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#define APLL_PDIV 0x6
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#define APLL_SDIV 0x1
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#define APLL_CON0_VAL SET_PLL(APLL_MDIV, APLL_PDIV, APLL_SDIV)
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/* APLL_CON1 */
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#define APLL_AFC_ENB 0x1
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#define APLL_AFC 0xC
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#define APLL_CON1_VAL ((APLL_AFC_ENB << 31) | (APLL_AFC << 0))
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/* MPLL_CON0 */
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#define MPLL_MDIV 0xC8
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#define MPLL_PDIV 0x6
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#define MPLL_SDIV 0x1
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#define MPLL_CON0_VAL SET_PLL(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV)
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/* MPLL_CON1 */
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#define MPLL_AFC_ENB 0x0
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#define MPLL_AFC 0x1C
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#define MPLL_CON1_VAL ((MPLL_AFC_ENB << 31) | (MPLL_AFC << 0))
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/* EPLL_CON0 */
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#define EPLL_MDIV 0x30
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#define EPLL_PDIV 0x3
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#define EPLL_SDIV 0x2
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#define EPLL_CON0_VAL SET_PLL(EPLL_MDIV, EPLL_PDIV, EPLL_SDIV)
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/* EPLL_CON1 */
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#define EPLL_K 0x0
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#define EPLL_CON1_VAL (EPLL_K >> 0)
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/* VPLL_CON0 */
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#define VPLL_MDIV 0x35
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#define VPLL_PDIV 0x3
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#define VPLL_SDIV 0x2
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#define VPLL_CON0_VAL SET_PLL(VPLL_MDIV, VPLL_PDIV, VPLL_SDIV)
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/* VPLL_CON1 */
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#define VPLL_SSCG_EN DISABLE
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#define VPLL_SEL_PF_DN_SPREAD 0x0
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#define VPLL_MRR 0x11
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#define VPLL_MFR 0x0
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#define VPLL_K 0x400
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#define VPLL_CON1_VAL ((VPLL_SSCG_EN << 31)\
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| (VPLL_SEL_PF_DN_SPREAD << 29) \
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| (VPLL_MRR << 24) \
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| (VPLL_MFR << 16) \
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| (VPLL_K << 0))
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/* DMC */
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#define DIRECT_CMD_NOP 0x07000000
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#define DIRECT_CMD_ZQ 0x0a000000
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#define DIRECT_CMD_CHIP1_SHIFT (1 << 20)
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#define MEM_TIMINGS_MSR_COUNT 4
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#define CTRL_START (1 << 0)
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#define CTRL_DLL_ON (1 << 1)
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#define AREF_EN (1 << 5)
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#define DRV_TYPE (1 << 6)
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struct mem_timings {
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unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
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unsigned timingref;
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unsigned timingrow;
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unsigned timingdata;
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unsigned timingpower;
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unsigned zqcontrol;
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unsigned control0;
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unsigned control1;
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unsigned control2;
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unsigned concontrol;
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unsigned prechconfig;
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unsigned memcontrol;
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unsigned memconfig0;
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unsigned memconfig1;
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unsigned dll_resync;
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unsigned dll_on;
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};
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/* MIU */
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/* MIU Config Register Offsets*/
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#define APB_SFR_INTERLEAVE_CONF_OFFSET 0x400
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#define APB_SFR_ARBRITATION_CONF_OFFSET 0xC00
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#define ABP_SFR_SLV_ADDRMAP_CONF_OFFSET 0x800
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#define ABP_SFR_INTERLEAVE_ADDRMAP_START_OFFSET 0x808
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#define ABP_SFR_INTERLEAVE_ADDRMAP_END_OFFSET 0x810
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#define ABP_SFR_SLV0_SINGLE_ADDRMAP_START_OFFSET 0x818
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#define ABP_SFR_SLV0_SINGLE_ADDRMAP_END_OFFSET 0x820
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#define ABP_SFR_SLV1_SINGLE_ADDRMAP_START_OFFSET 0x828
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#define ABP_SFR_SLV1_SINGLE_ADDRMAP_END_OFFSET 0x830
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#ifdef CONFIG_TARGET_ORIGEN
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/* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */
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#define APB_SFR_INTERLEAVE_CONF_VAL 0x20001507
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#define APB_SFR_ARBRITATION_CONF_VAL 0x00000001
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#endif
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#define INTERLEAVE_ADDR_MAP_START_ADDR 0x40000000
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#define INTERLEAVE_ADDR_MAP_END_ADDR 0xbfffffff
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#define INTERLEAVE_ADDR_MAP_EN 0x00000001
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#ifdef CONFIG_MIU_1BIT_INTERLEAVED
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/* Interleave_bit0: 0xC*/
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#define APB_SFR_INTERLEAVE_CONF_VAL 0x0000000c
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#endif
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#ifdef CONFIG_MIU_2BIT_INTERLEAVED
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/* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0xc */
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#define APB_SFR_INTERLEAVE_CONF_VAL 0x2000150c
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#endif
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#define SLAVE0_SINGLE_ADDR_MAP_START_ADDR 0x40000000
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#define SLAVE0_SINGLE_ADDR_MAP_END_ADDR 0x7fffffff
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#define SLAVE1_SINGLE_ADDR_MAP_START_ADDR 0x80000000
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#define SLAVE1_SINGLE_ADDR_MAP_END_ADDR 0xbfffffff
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/* Enable SME0 and SME1*/
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#define APB_SFR_SLV_ADDR_MAP_CONF_VAL 0x00000006
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#define FORCE_DLL_RESYNC 3
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#define DLL_CONTROL_ON 1
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#define DIRECT_CMD1 0x00020000
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#define DIRECT_CMD2 0x00030000
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#define DIRECT_CMD3 0x00010002
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#define DIRECT_CMD4 0x00000328
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#define CTRL_ZQ_MODE_NOTERM (0x1 << 0)
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#define CTRL_ZQ_START (0x1 << 1)
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#define CTRL_ZQ_DIV (0 << 4)
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#define CTRL_ZQ_MODE_DDS (0x7 << 8)
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#define CTRL_ZQ_MODE_TERM (0x2 << 11)
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#define CTRL_ZQ_FORCE_IMPN (0x5 << 14)
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#define CTRL_ZQ_FORCE_IMPP (0x6 << 17)
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#define CTRL_DCC (0xE38 << 20)
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#define ZQ_CONTROL_VAL (CTRL_ZQ_MODE_NOTERM | CTRL_ZQ_START\
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| CTRL_ZQ_DIV | CTRL_ZQ_MODE_DDS\
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| CTRL_ZQ_MODE_TERM | CTRL_ZQ_FORCE_IMPN\
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| CTRL_ZQ_FORCE_IMPP | CTRL_DCC)
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#define ASYNC (0 << 0)
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#define CLK_RATIO (1 << 1)
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#define DIV_PIPE (1 << 3)
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#define AWR_ON (1 << 4)
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#define AREF_DISABLE (0 << 5)
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#define DRV_TYPE_DISABLE (0 << 6)
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#define CHIP0_NOT_EMPTY (0 << 8)
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#define CHIP1_NOT_EMPTY (0 << 9)
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#define DQ_SWAP_DISABLE (0 << 10)
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#define QOS_FAST_DISABLE (0 << 11)
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#define RD_FETCH (0x3 << 12)
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#define TIMEOUT_LEVEL0 (0xFFF << 16)
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#define CONCONTROL_VAL (ASYNC | CLK_RATIO | DIV_PIPE | AWR_ON\
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| AREF_DISABLE | DRV_TYPE_DISABLE\
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| CHIP0_NOT_EMPTY | CHIP1_NOT_EMPTY\
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| DQ_SWAP_DISABLE | QOS_FAST_DISABLE\
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| RD_FETCH | TIMEOUT_LEVEL0)
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#define CLK_STOP_DISABLE (0 << 1)
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#define DPWRDN_DISABLE (0 << 2)
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#define DPWRDN_TYPE (0 << 3)
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#define TP_DISABLE (0 << 4)
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#define DSREF_DIABLE (0 << 5)
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#define ADD_LAT_PALL (1 << 6)
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#define MEM_TYPE_DDR3 (0x6 << 8)
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#define MEM_WIDTH_32 (0x2 << 12)
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#define NUM_CHIP_2 (1 << 16)
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#define BL_8 (0x3 << 20)
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#define MEMCONTROL_VAL (CLK_STOP_DISABLE | DPWRDN_DISABLE\
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| DPWRDN_TYPE | TP_DISABLE | DSREF_DIABLE\
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| ADD_LAT_PALL | MEM_TYPE_DDR3 | MEM_WIDTH_32\
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| NUM_CHIP_2 | BL_8)
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#define CHIP_BANK_8 (0x3 << 0)
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#define CHIP_ROW_14 (0x2 << 4)
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#define CHIP_COL_10 (0x3 << 8)
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#define CHIP_MAP_INTERLEAVED (1 << 12)
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#define CHIP_MASK (0xe0 << 16)
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#ifdef CONFIG_MIU_LINEAR
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#define CHIP0_BASE (0x40 << 24)
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#define CHIP1_BASE (0x60 << 24)
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#else
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#define CHIP0_BASE (0x20 << 24)
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#define CHIP1_BASE (0x40 << 24)
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#endif
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#define MEMCONFIG0_VAL (CHIP_BANK_8 | CHIP_ROW_14 | CHIP_COL_10\
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| CHIP_MAP_INTERLEAVED | CHIP_MASK | CHIP0_BASE)
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#define MEMCONFIG1_VAL (CHIP_BANK_8 | CHIP_ROW_14 | CHIP_COL_10\
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| CHIP_MAP_INTERLEAVED | CHIP_MASK | CHIP1_BASE)
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#define TP_CNT (0xff << 24)
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#define PRECHCONFIG TP_CNT
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#define CTRL_OFF (0 << 0)
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#define CTRL_DLL_OFF (0 << 1)
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#define CTRL_HALF (0 << 2)
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#define CTRL_DFDQS (1 << 3)
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#define DQS_DELAY (0 << 4)
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#define CTRL_START_POINT (0x10 << 8)
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#define CTRL_INC (0x10 << 16)
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#define CTRL_FORCE (0x71 << 24)
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#define CONTROL0_VAL (CTRL_OFF | CTRL_DLL_OFF | CTRL_HALF\
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|
| CTRL_DFDQS | DQS_DELAY | CTRL_START_POINT\
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| CTRL_INC | CTRL_FORCE)
|
|
|
|
#define CTRL_SHIFTC (0x6 << 0)
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|
#define CTRL_REF (8 << 4)
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|
#define CTRL_SHGATE (1 << 29)
|
|
#define TERM_READ_EN (1 << 30)
|
|
#define TERM_WRITE_EN (1 << 31)
|
|
#define CONTROL1_VAL (CTRL_SHIFTC | CTRL_REF | CTRL_SHGATE\
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|
| TERM_READ_EN | TERM_WRITE_EN)
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|
|
|
#define CONTROL2_VAL 0x00000000
|
|
|
|
#ifdef CONFIG_TARGET_ORIGEN
|
|
#define TIMINGREF_VAL 0x000000BB
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|
#define TIMINGROW_VAL 0x4046654f
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|
#define TIMINGDATA_VAL 0x46400506
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|
#define TIMINGPOWER_VAL 0x52000A3C
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|
#else
|
|
#define TIMINGREF_VAL 0x000000BC
|
|
#define TIMINGROW_VAL 0x45430506
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|
#define TIMINGDATA_VAL 0x56500506
|
|
#define TIMINGPOWER_VAL 0x5444033d
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|
#endif
|
|
#endif
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