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The registers which are managed by the meson-gxl-usb3 PHY driver are actually "USB control" registers (which are "glue" registers which manage OTG detection and routing of the OTG capable port between the DWC2 peripheral-only controller and the DWC3 host-only controller). Drop the meson-gxl-usb3 PHY driver now that the dwc3-meson-gxl-usb driver supports the USB control registers on GXL and GXM SoCs (these were previously managed by the meson-gxl-usb3 PHY driver). Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
18 lines
445 B
C
18 lines
445 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2019 BayLibre SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*/
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#ifndef _ARCH_MESON_USB_GX_H_
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#define _ARCH_MESON_USB_GX_H_
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#include <generic-phy.h>
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#include <linux/usb/otg.h>
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/* TOFIX add set_mode to struct phy_ops */
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void phy_meson_gxl_usb2_set_mode(struct phy *phy, enum usb_dr_mode mode);
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int dwc3_meson_gxl_force_mode(struct udevice *dev, enum usb_dr_mode mode);
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#endif
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