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4bc0104c97
This patch adds support for MediaTek MT7621 SoC. All files are dedicated for u-boot. The default build target is u-boot-mt7621.bin. The specification of this chip: https://www.mediatek.com/products/homenetworking/mt7621 Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
101 lines
2.3 KiB
C
101 lines
2.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2022 MediaTek Inc. All rights reserved.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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#include <asm/io.h>
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#include <asm/cm.h>
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#include <asm/sections.h>
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#include <asm/addrspace.h>
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#include <asm/mipsmtregs.h>
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#include <linux/sizes.h>
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#include <time.h>
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#include <cpu_func.h>
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#include "launch.h"
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#include "../mt7621.h"
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/* Cluster Power Controller (CPC) offsets */
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#define CPC_CL_OTHER 0x2010
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#define CPC_CO_CMD 0x4000
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/* CPC_CL_OTHER fields */
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#define CPC_CL_OTHER_CORENUM_SHIFT 16
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#define CPC_CL_OTHER_CORENUM GENMASK(23, 16)
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/* CPC_CO_CMD */
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#define PWR_UP 3
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#define NUM_CORES 2
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#define NUM_CPUS 4
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#define WAIT_CPUS_TIMEOUT 4000
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static void copy_launch_wait_code(void)
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{
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memset((void *)KSEG1, 0, SZ_4K);
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memcpy((void *)KSEG1ADDR(LAUNCH_WAITCODE),
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&launch_wait_code_start,
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&launch_wait_code_end - &launch_wait_code_start);
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invalidate_dcache_range(KSEG0, SZ_4K);
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}
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static void bootup_secondary_core(void)
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{
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void __iomem *cpcbase = (void __iomem *)KSEG1ADDR(MIPS_CPC_BASE);
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int i;
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for (i = 1; i < NUM_CORES; i++) {
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writel(i << CPC_CL_OTHER_CORENUM_SHIFT, cpcbase + CPC_CL_OTHER);
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writel(PWR_UP, cpcbase + CPC_CO_CMD);
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}
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}
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void secondary_cpu_init(void)
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{
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void __iomem *sysc = (void __iomem *)KSEG1ADDR(SYSCTL_BASE);
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u32 i, dual_core = 0, cpuready = 1, cpumask = 0x03;
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ulong wait_tick;
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struct cpulaunch_t *c;
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/* Copy LAUNCH wait code used by other VPEs */
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copy_launch_wait_code();
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dual_core = readl(sysc + SYSCTL_CHIP_REV_ID_REG) & CPU_ID;
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if (dual_core) {
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/* Bootup secondary core for MT7621A */
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cpumask = 0x0f;
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/* Make BootROM/TPL redirect Core1's bootup flow to our entry point */
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writel((uintptr_t)&_start, sysc + BOOT_SRAM_BASE_REG);
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bootup_secondary_core();
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}
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/* Join the coherent domain */
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join_coherent_domain(dual_core ? 2 : 1);
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/* Bootup Core0/VPE1 */
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boot_vpe1();
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/* Wait for all CPU ready */
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wait_tick = get_timer(0) + WAIT_CPUS_TIMEOUT;
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while (time_before(get_timer(0), wait_tick)) {
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/* CPU0 is obviously ready */
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for (i = 1; i < NUM_CPUS; i++) {
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c = (struct cpulaunch_t *)(KSEG0ADDR(CPULAUNCH) +
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(i << LOG2CPULAUNCH));
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if (c->flags & LAUNCH_FREADY)
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cpuready |= BIT(i);
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}
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if ((cpuready & cpumask) == cpumask)
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break;
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}
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}
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