mirror of
https://github.com/smaeul/u-boot.git
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5da627a424
- Add support for Altera FPGA ACEX1K
* Patches by Thomas Lange, 09 Oct 2003:
- Endian swap ATA identity for all big endian CPUs, not just PPC
- MIPS only: New option CONFIG_MEMSIZE_IN_BYTES for passing memsize
args to linux
- add support for dbau1x00 board (MIPS32)
372 lines
8.8 KiB
C
372 lines
8.8 KiB
C
/*
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* (INCA) ASC UART support
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*/
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#include <config.h>
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#if defined(CONFIG_PURPLE) || defined(CONFIG_INCA_IP)
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#ifdef CONFIG_PURPLE
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#define serial_init asc_serial_init
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#define serial_putc asc_serial_putc
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#define serial_puts asc_serial_puts
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#define serial_getc asc_serial_getc
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#define serial_tstc asc_serial_tstc
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#define serial_setbrg asc_serial_setbrg
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#endif
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#include <common.h>
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#include <asm/inca-ip.h>
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#include "asc_serial.h"
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#ifdef CONFIG_PURPLE
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#undef ASC_FIFO_PRESENT
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#define TOUT_LOOP 100000
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/* Set base address for second FPI interrupt control register bank */
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#define SFPI_INTCON_BASEADDR 0xBF0F0000
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/* Register offset from base address */
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#define FBS_ISR 0x00000000 /* Interrupt status register */
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#define FBS_IMR 0x00000008 /* Interrupt mask register */
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#define FBS_IDIS 0x00000010 /* Interrupt disable register */
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/* Interrupt status register bits */
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#define FBS_ISR_AT 0x00000040 /* ASC transmit interrupt */
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#define FBS_ISR_AR 0x00000020 /* ASC receive interrupt */
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#define FBS_ISR_AE 0x00000010 /* ASC error interrupt */
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#define FBS_ISR_AB 0x00000008 /* ASC transmit buffer interrupt */
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#define FBS_ISR_AS 0x00000004 /* ASC start of autobaud detection interrupt */
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#define FBS_ISR_AF 0x00000002 /* ASC end of autobaud detection interrupt */
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#else
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#define ASC_FIFO_PRESENT
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#endif
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#define SET_BIT(reg, mask) reg |= (mask)
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#define CLEAR_BIT(reg, mask) reg &= (~mask)
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#define CLEAR_BITS(reg, mask) CLEAR_BIT(reg, mask)
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#define SET_BITS(reg, mask) SET_BIT(reg, mask)
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#define SET_BITFIELD(reg, mask, off, val) {reg &= (~mask); reg |= (val << off);}
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extern uint incaip_get_fpiclk(void);
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static int serial_setopt (void);
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/* pointer to ASC register base address */
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static volatile incaAsc_t *pAsc = (incaAsc_t *)INCA_IP_ASC;
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/******************************************************************************
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*
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* serial_init - initialize a INCAASC channel
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*
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* This routine initializes the number of data bits, parity
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* and set the selected baud rate. Interrupts are disabled.
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* Set the modem control signals if the option is selected.
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*
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* RETURNS: N/A
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*/
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int serial_init (void)
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{
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#ifdef CONFIG_INCA_IP
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/* we have to set PMU.EN13 bit to enable an ASC device*/
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INCAASC_PMU_ENABLE(13);
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#endif
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/* and we have to set CLC register*/
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CLEAR_BIT(pAsc->asc_clc, ASCCLC_DISS);
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SET_BITFIELD(pAsc->asc_clc, ASCCLC_RMCMASK, ASCCLC_RMCOFFSET, 0x0001);
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/* initialy we are in async mode */
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pAsc->asc_con = ASCCON_M_8ASYNC;
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/* select input port */
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pAsc->asc_pisel = (CONSOLE_TTY & 0x1);
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#ifdef ASC_FIFO_PRESENT
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/* TXFIFO's filling level */
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SET_BITFIELD(pAsc->asc_txfcon, ASCTXFCON_TXFITLMASK,
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ASCTXFCON_TXFITLOFF, INCAASC_TXFIFO_FL);
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/* enable TXFIFO */
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SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXFEN);
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/* RXFIFO's filling level */
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SET_BITFIELD(pAsc->asc_txfcon, ASCRXFCON_RXFITLMASK,
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ASCRXFCON_RXFITLOFF, INCAASC_RXFIFO_FL);
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/* enable RXFIFO */
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SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXFEN);
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#endif
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/* enable error signals */
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SET_BIT(pAsc->asc_con, ASCCON_FEN);
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SET_BIT(pAsc->asc_con, ASCCON_OEN);
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#ifdef CONFIG_INCA_IP
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/* acknowledge ASC interrupts */
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ASC_INTERRUPTS_CLEAR(INCAASC_IRQ_LINE_ALL);
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/* disable ASC interrupts */
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ASC_INTERRUPTS_DISABLE(INCAASC_IRQ_LINE_ALL);
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#endif
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#ifdef ASC_FIFO_PRESENT
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/* set FIFOs into the transparent mode */
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SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXTMEN);
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SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXTMEN);
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#endif
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/* set baud rate */
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serial_setbrg();
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/* set the options */
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serial_setopt();
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return 0;
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}
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void serial_setbrg (void)
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{
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ulong uiReloadValue, fdv;
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ulong f_ASC;
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#ifdef CONFIG_INCA_IP
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f_ASC = incaip_get_fpiclk();
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#else
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f_ASC = ASC_CLOCK_RATE;
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#endif
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#ifndef INCAASC_USE_FDV
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fdv = 2;
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uiReloadValue = (f_ASC / (fdv * 16 * CONFIG_BAUDRATE)) - 1;
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#else
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fdv = INCAASC_FDV_HIGH_BAUDRATE;
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uiReloadValue = (f_ASC / (8192 * CONFIG_BAUDRATE / fdv)) - 1;
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#endif /* INCAASC_USE_FDV */
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if ( (uiReloadValue < 0) || (uiReloadValue > 8191) )
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{
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#ifndef INCAASC_USE_FDV
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fdv = 3;
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uiReloadValue = (f_ASC / (fdv * 16 * CONFIG_BAUDRATE)) - 1;
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#else
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fdv = INCAASC_FDV_LOW_BAUDRATE;
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uiReloadValue = (f_ASC / (8192 * CONFIG_BAUDRATE / fdv)) - 1;
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#endif /* INCAASC_USE_FDV */
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if ( (uiReloadValue < 0) || (uiReloadValue > 8191) )
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{
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return; /* can't impossibly generate that baud rate */
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}
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}
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/* Disable Baud Rate Generator; BG should only be written when R=0 */
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CLEAR_BIT(pAsc->asc_con, ASCCON_R);
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#ifndef INCAASC_USE_FDV
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/*
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* Disable Fractional Divider (FDE)
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* Divide clock by reload-value + constant (BRS)
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*/
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/* FDE = 0 */
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CLEAR_BIT(pAsc->asc_con, ASCCON_FDE);
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if ( fdv == 2 )
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CLEAR_BIT(pAsc->asc_con, ASCCON_BRS); /* BRS = 0 */
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else
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SET_BIT(pAsc->asc_con, ASCCON_BRS); /* BRS = 1 */
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#else /* INCAASC_USE_FDV */
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/* Enable Fractional Divider */
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SET_BIT(pAsc->asc_con, ASCCON_FDE); /* FDE = 1 */
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/* Set fractional divider value */
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pAsc->asc_fdv = fdv & ASCFDV_VALUE_MASK;
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#endif /* INCAASC_USE_FDV */
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/* Set reload value in BG */
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pAsc->asc_bg = uiReloadValue;
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/* Enable Baud Rate Generator */
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SET_BIT(pAsc->asc_con, ASCCON_R); /* R = 1 */
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}
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/*******************************************************************************
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*
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* serial_setopt - set the serial options
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*
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* Set the channel operating mode to that specified. Following options
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* are supported: CREAD, CSIZE, PARENB, and PARODD.
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*
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* Note, this routine disables the transmitter. The calling routine
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* may have to re-enable it.
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*
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* RETURNS:
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* Returns 0 to indicate success, otherwise -1 is returned
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*/
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static int serial_setopt (void)
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{
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ulong con;
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switch ( ASC_OPTIONS & ASCOPT_CSIZE )
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{
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/* 7-bit-data */
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case ASCOPT_CS7:
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con = ASCCON_M_7ASYNCPAR; /* 7-bit-data and parity bit */
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break;
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/* 8-bit-data */
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case ASCOPT_CS8:
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if ( ASC_OPTIONS & ASCOPT_PARENB )
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con = ASCCON_M_8ASYNCPAR; /* 8-bit-data and parity bit */
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else
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con = ASCCON_M_8ASYNC; /* 8-bit-data no parity */
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break;
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/*
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* only 7 and 8-bit frames are supported
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* if we don't use IOCTL extensions
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*/
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default:
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return -1;
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}
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if ( ASC_OPTIONS & ASCOPT_STOPB )
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SET_BIT(con, ASCCON_STP); /* 2 stop bits */
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else
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CLEAR_BIT(con, ASCCON_STP); /* 1 stop bit */
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if ( ASC_OPTIONS & ASCOPT_PARENB )
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SET_BIT(con, ASCCON_PEN); /* enable parity checking */
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else
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CLEAR_BIT(con, ASCCON_PEN); /* disable parity checking */
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if ( ASC_OPTIONS & ASCOPT_PARODD )
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SET_BIT(con, ASCCON_ODD); /* odd parity */
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else
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CLEAR_BIT(con, ASCCON_ODD); /* even parity */
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if ( ASC_OPTIONS & ASCOPT_CREAD )
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SET_BIT(pAsc->asc_whbcon, ASCWHBCON_SETREN); /* Receiver enable */
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pAsc->asc_con |= con;
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return 0;
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}
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void serial_putc (const char c)
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{
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#ifdef ASC_FIFO_PRESENT
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uint txFl = 0;
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#else
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uint timeout = 0;
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#endif
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if (c == '\n') serial_putc ('\r');
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#ifdef ASC_FIFO_PRESENT
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/* check do we have a free space in the TX FIFO */
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/* get current filling level */
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do
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{
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txFl = ( pAsc->asc_fstat & ASCFSTAT_TXFFLMASK ) >> ASCFSTAT_TXFFLOFF;
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}
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while ( txFl == INCAASC_TXFIFO_FULL );
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#else
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while(!(*(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) &
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FBS_ISR_AB))
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{
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if (timeout++ > TOUT_LOOP)
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{
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break;
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}
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}
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#endif
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pAsc->asc_tbuf = c; /* write char to Transmit Buffer Register */
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#ifndef ASC_FIFO_PRESENT
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*(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) = FBS_ISR_AB |
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FBS_ISR_AT;
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#endif
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/* check for errors */
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if ( pAsc->asc_con & ASCCON_OE )
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{
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SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLROE);
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return;
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}
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}
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void serial_puts (const char *s)
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{
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while (*s)
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{
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serial_putc (*s++);
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}
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}
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int serial_getc (void)
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{
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ulong symbol_mask;
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char c;
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while (!serial_tstc());
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symbol_mask =
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((ASC_OPTIONS & ASCOPT_CSIZE) == ASCOPT_CS7) ? (0x7f) : (0xff);
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c = (char)(pAsc->asc_rbuf & symbol_mask);
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#ifndef ASC_FIFO_PRESENT
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*(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) = FBS_ISR_AR;
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#endif
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return c;
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}
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int serial_tstc (void)
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{
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int res = 1;
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#ifdef ASC_FIFO_PRESENT
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if ( (pAsc->asc_fstat & ASCFSTAT_RXFFLMASK) == 0 )
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{
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res = 0;
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}
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#else
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if (!(*(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) &
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FBS_ISR_AR))
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{
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res = 0;
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}
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#endif
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else if ( pAsc->asc_con & ASCCON_FE )
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{
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SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRFE);
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res = 0;
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}
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else if ( pAsc->asc_con & ASCCON_PE )
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{
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SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRPE);
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res = 0;
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}
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else if ( pAsc->asc_con & ASCCON_OE )
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{
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SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLROE);
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res = 0;
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}
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return res;
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}
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#endif /* CONFIG_PURPLE || CONFIG_INCA_IP */
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