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ce39680f7e
Provide the specific addresses for the Chip ID and Chip ID Extension registers, instead of the offset, which make it use on other chips. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
39 lines
979 B
C
39 lines
979 B
C
/*
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* Copyright (C) 2010
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* Reinhard Meyer, reinhard.meyer@emk-elektronik.de
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*
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* Debug Unit
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* Based on AT91SAM9XE datasheet
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef AT91_DBU_H
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#define AT91_DBU_H
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#ifndef __ASSEMBLY__
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typedef struct at91_dbu {
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u32 cr; /* Control Register WO */
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u32 mr; /* Mode Register RW */
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u32 ier; /* Interrupt Enable Register WO */
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u32 idr; /* Interrupt Disable Register WO */
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u32 imr; /* Interrupt Mask Register RO */
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u32 sr; /* Status Register RO */
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u32 rhr; /* Receive Holding Register RO */
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u32 thr; /* Transmit Holding Register WO */
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u32 brgr; /* Baud Rate Generator Register RW */
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u32 res1[7];/* 0x0024 - 0x003C Reserved */
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u32 cidr; /* Chip ID Register RO */
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u32 exid; /* Chip ID Extension Register RO */
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u32 fnr; /* Force NTRST Register RW */
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} at91_dbu_t;
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#endif /* __ASSEMBLY__ */
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#define AT91_DBU_CID_ARCH_MASK 0x0ff00000
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#define AT91_DBU_CID_ARCH_9xx 0x01900000
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#define AT91_DBU_CID_ARCH_9XExx 0x02900000
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#endif
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